A Composable AI-Accelerated Iterative Solver for 3D-IC Thermal Modeling

Yixing Li; Jiahang Zhou; Zhiyu Zeng; Xin Ai

cs.LGOct 1, 2026

A Composable AI-Accelerated Iterative Solver for 3D-IC Thermal Modeling

Authors: Yixing Li, Jiahang Zhou, Zhiyu Zeng, Xin Ai

Organizations: Cadence Design Systems · University of Notre Dame

Abstract

Accurate thermal analysis of heterogeneous 2.5D/3D-IC packages is essential yet computationally prohibitive. A single full-package FEM simulation can take hours, while AI-based surrogates treat the entire stack as a monolithic prediction target and must be retrained whenever the die count or topology changes. To address this limitation, this work proposes Domain-Decomposed AI-Accelerated Iterative Solver for Thermal Analysis (DAIST), a composable thermal solver that decomposes the global package simulation into block-level subdomain problems, replaces subdomain solvers with neural operators, and couples them through iterative exchanges of interfacial temperature and heat flux. This local-to-global architecture eliminates the topology lock-in of monolithic models: block-level neural operators can be directly reused in unseen package assemblies without retraining. The iterative coupling strategy further provides a controllable accuracy-runtime tradeoff, where the iteration budget can be adjusted to trade accuracy for runtime. Evaluated on a multi-chiplet system and an advanced packaging system, DAIST achieves up to $178\times$ speedup over traditional FEM solvers with mean temperature errors of 0.068% and 0.323%, respectively, while demonstrating cross-topology reuse of block-level models across structurally distinct package assemblies.

Figures & tables

Panel of Figure 1 — Fig. 1: Overview of the DAIST two-phase algorithm. Interface iteration (left): each block’s AI model predicts surface temperature and heat flux, and interface quantities are exchanged between neighboring blocks with relaxation parameter $\omega$ . The process repeats until convergence ( $\delta^{(k)}<\tau$ ). Field reconstruction (right): a single forward pass per block produces the full three-layer temperature field, which is assembled into the global solution field $T(\mathbf{x})$ .

Fig. 2: Representative stackup schematics (not to scale) for the multi-chiplet assembly (Interposer–SoC–HBM, left) and the advanced packaging assembly (Interposer–MC–TIM, right): planar SoC and HBM placements on the shared interposer versus a vertical stack of molding compound (MC) and thermal interface material (TIM), consistent with the block parameters in Table I .

Case I: Multi-chiplet system (Interposer–SoC–HBM)
Block	Orientation	No. components	Footprint ‡	Thickness ( $\mu$ m) †	$k$ (W/m $\cdot$ K) †	Power (W) † ∗
Interposer	face up	$1$	$5\times 5$ mm	$(100,\ 1,\ 1)$	$(100,\ 2.175,\ 0.3)$	$(0,\ 0,\ 0)$
SoC	face down	$[1,\ 3]$	$2\times 1$ mm	$(10,\ 1,\ 1)$	$(100,\ 2.175,\ 0.3)$	$(0,\ [0.05,0.1],\ 0)$
HBM	face down	$[1,\ 10]$	$0.5\times 0.4$ mm	$(20,\ 1,\ 1)$	$(100,\ 2.175,\ 0.3)$	$(0,\ [0.01,0.03],\ 0)$
Case II: Advanced packaging system (Interposer–MC–TIM)
Interposer	face up	$1$	$5\times 5$ mm	$(100,\ 1,\ 1)$	$(100,\ 2.175,\ 0.3)$	$(0,\ 0,\ 0)$

TABLE I: Block geometry and material parameters for Multi-chiplet System and Advanced Packaging System.

Fig. 3: Three-dimensional thermal visualization of the multi-chiplet assembly (Interposer–SoC–HBM). Left: Celsius Thermal Solver reference. Center: DAIST prediction. Right: pointwise absolute error.

Method	MAE (K)	Max (K)	Runtime (s)	Speedup
Celsius reference	—	—	$146$	$1\times$
DAIST	$\mathbf{0.253}$	$\mathbf{1.135}$	$0.82$	$\mathbf{178\times}$

TABLE II: Accuracy and runtime comparison on the multi-chiplet system.

Iterations	Mean MAE (K)	Wall time ∗
$1$	$4.228$	$0.328$
$2$	$3.398$	$0.445$
$3$	$1.769$	$0.562$
$4$	$0.757$	$0.679$
$5$	$0.290$	$0.796$
$6$	$0.168$	$0.913$

TABLE III: Mean MAE and wall time at fixed iteration counts for multi-chiplet test set.

Fig. 4: Interface residual $\delta^{(k)}$ vs. coupling iteration for both case studies. The dashed line marks the convergence tolerance $\tau=0.1\%$ .

Method	Test Set	Runtime (s)	MAE (K)	Max (K)	MAPE	RMSE (K)
DAIST	Fixed-topology	$0.82$	$\mathbf{0.282}$	$1.230$	$7.01\times 10^{-4}$	$0.356$
DAIST	Variable-topology	$0.82$	$\mathbf{0.351}$	$\mathbf{1.233}$	$9.10\times 10^{-4}$	$0.415$
Monolithic	Fixed-topology	$0.12$	$0.433$	$\mathbf{0.937}$	$1.07\times 10^{-3}$	$0.474$
Monolithic	Variable-topology	$0.12$	$26.264$	$26.944$	$6.83\times 10^{-2}$	$26.269$

TABLE IV: Accuracy and runtime comparison of DAIST and the monolithic neural predictor on fixed-topology and variable-topology test sets.

\dagger

Fig. 5: Out-of-distribution comparison on a variable-topology case. Left to right: Celsius Thermal Solver reference, DAIST prediction, monolithic prediction, DAIST error, monolithic error.

Block	Trained on	Tested in
Interposer	SoC–HBM (frozen)	MC–TIM
MC	MC–TIM	MC–TIM
TIM	MC–TIM	MC–TIM

TABLE V: Cross-topology block reuse: training and testing configurations. The interposer model is frozen from the multi-chiplet system and receives no MC–TIM training data.

Fig. 6: Three-dimensional thermal visualization of the advanced packaging assembly (Interposer–MC–TIM) with a frozen interposer model transferred from the multi-chiplet system. Left: Celsius Thermal Solver reference. Center: DAIST prediction. Right: pointwise error.

Iterations	Mean MAE (K)	Wall time (s)
$1$	$33.282$	$0.328$
$5$	$5.657$	$0.796$
$10$	$1.914$	$1.381$
$15$	$1.239$	$1.966$
$20$	$0.997$	$2.551$
Celsius reference	—	$197$

TABLE VI: Mean MAE and wall time at fixed iteration counts for advanced packaging test set.

Domain Decomposition Methods

See all 15 papers

DeepOHeat-v2: Self-Improving Operator Learning for Fast and Trustworthy Thermal Optimization in 3D-IC Design
Aug 17, 2026Xinling Yu, Yixing Li, Ziyue Liu +4PDE Operator Learning Surrogate-Assisted Optimization
Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106 USA · Cadence Design Systems, Austin, TX 78759 USA · Department of Computer Science, University of California, Santa Barbara, CA 93106 USA +1
AI for Science with GPT-6 Astra: Thermal Design and Electrothermal Analysis of 2D CFET
Sep 15, 2026Min-Hui Kim, Khushi Sharma, Sarah Zhang +1
Graduate School of Semiconductor Materials and Devices, Ulsan National Institute of Science and Technology (UNIST), Ulsan 44919, Republic of Korea · Materials Science and Engineering, National University of Singapore, Singapore · Materials Science and Engineering, Cornell University, Ithaca, NY, USA +1
Recursive transformers for semiconductor thermo-mechanical reliability
Jul 28, 2026Kart-leong LimNeural Surrogate Modeling PDE Surrogate Modeling
Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore

Aug 17, 2026J/K move · Enter open · S save

DeepOHeat-v2: Self-Improving Operator Learning for Fast and Trustworthy Thermal Optimization in 3D-IC Design

Xinling Yu, Yixing Li, Ziyue Liu, Xin Ai+3

Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106 USA · Cadence Design Systems, Austin, TX 78759 USA · Department of Computer Science, University of California, Santa Barbara, CA 93106 USA+1

PDE Operator Learning Surrogate-Assisted Optimization Physics-Informed Neural Operators

Open paper AskPDF arXiv

Thermal-aware optimization of multi-die 3D integrated circuits evaluates many designs, each a costly heat-equation solve. Operator-learning surrogates replace this solve with a fast forward pass, ideally trained from physics alone, without labeled data. DeepOHeat-v1 made such surrogates fast and trustworthy, but only on low-contrast geometries. High-contrast multi-die stacks break it in two ways: discontinuous conductivities make the continuous physics loss ill-defined at material interfaces, and ill-conditioning (

κ_2(A_h) \approx 6 \times 10^4

) puts the discretized strong-form loss beyond first-order optimization. We propose DeepOHeat-v2 to overcome both. First, we train on a discretized physics loss that handles the discontinuities natively; its energy form reduces the prediction-space loss-Hessian conditioning from

κ^2

κ

, and a matrix-preconditioned optimizer cuts the mean peak temperature error from over 30 K to 0.55 K. Second, because optimization leaves the training distribution, we propose a self-improving framework: a hotspot trust gate sends flagged placements to a reference solver, and the surrogate incrementally retrains on the refined solutions, keeping an update only when it improves held-out validation error. On a multi-die benchmark, the surrogate-true peak gap on the returned design falls from 1.12 K to 0.11 K, matching a solve-at-every-step optimizer while running

56\times

faster.

Abstract

Domain Decomposition Methods

Explore similar work

DeepOHeat-v2: Self-Improving Operator Learning for Fast and Trustworthy Thermal Optimization in 3D-IC Design

AI for Science with GPT-6 Astra: Thermal Design and Electrothermal Analysis of 2D CFET

Recursive transformers for semiconductor thermo-mechanical reliability