Back to the Future: Rethinking EDA Infrastructure for Agentic Systems in Chip Design Verification
Organizations: Department of Computer Science Columbia University New York, NY, USA · Google Mountain View, CA, USA
Abstract
The unprecedented computational scale of modern artificial intelligence depends on complex, multi-billion-transistor Systems-on-Chip, yet the workflows that verify these chips remain stubbornly manual. Although Large Language Models (LLMs) have made rapid inroads into Electronic Design Automation (EDA), approximately 74.6% of existing studies target static Register-Transfer Level (RTL) code generation, leaving post-simulation verification and interactive waveform debugging largely untouched. We introduce Back-to-the-Future (BTTF), an end-to-end agentic framework that closes this infrastructural gap. BTTF distills massive, unstructured simulation dumps into a normalized relational SQLite database and couples it with a collaborative multi-agent orchestration engine that translates natural-language verification queries into schema-aware SQL while correlating signal anomalies with versioned RTL repositories. Across a 150-query benchmark, BTTF attains 95.33% execution accuracy, charting a practical path toward autonomous EDA verification.
Figures & tables
| Domain | Task / Query Type | Example Natural Language Query | Accuracy |
| Debugging | Scope/Net Discovery | “List all logics in the moduleA .” | 100.00% |
| RTL Attribution | “Find the RTL file related to logicA .” | 87.50% | |
| Value Inspection | “What is the value of logicA at time timeA ?” | 95.00% | |
| Value Change Count | “How many times has logicA changed?” | 100.00% | |
| Event Timing Check | “When is net logicA first set to valueA ?” | 100.00% | |
| Analyzing | Toggle Coverage | “Calculate overall toggle coverage in jobA.db .” | 91.67% |
Appendix figures & tables1 asset
Supplementary material from the paper’s appendix.
Appendix
| Domain | Task / Query Type | Natural Language User Query | Agent Action with Tool Invocation Generated Output Response |
|---|---|---|---|
| Debugging | Scope/Net Discovery | “List all the nets in moduleA .” | Action: find_signal_in_scope(db, "moduleA") Output: ["bank_id", "bank_addr"] (Found 2 struct field signals) |
| Signal Scope Discovery | “What is the scope name of the signal port_id ?” | Action: find_scope_by_signal_name(db, "port_id") Output: moduleA_ep_{leaf, master, follower}_id | |
| RTL Attribution | “Find the RTL file related to signal signalA.cnt .” | Action: find_source_module("soc_top", ".../moduleA/rtl/", "cnt") Output: design/.../moduleA.sv:L142 ( logic [7:0] cnt ) | |
| Value Inspection | “What is the value of signal ctrl_status at time 7155316?” | Action: get_value_of_signal_at_time(db, "ctrl_status", 7155316) Output: Value: 8184 ( 0x1FF8 in hex) at | |
| Value Change Count | “What is the number of toggles of credit_stall ?” | Action: get_signal_toggle(db, "credit_stall", 6800000, 8000000) Output: 4 toggles across simulation window | |
| Event Timing Check | “When is the first time the signal req_accept[7] is set to 42?” | Action: get_first_time_of_signal_value(db, "req_accept[7]", "42", 181.5us, 184us) Output: First transition detected at ( 182031570 ps ) |