Chip Design

Follow this topic Ask about this topic

Momentum

5 papers in the last four weeks, up 25% on the four weeks before. 0.0% of all new papers.

Jul 13Week of Sep 28

Latest papers 52

All topics

Validity-Preserving Hierarchical RL for Joint Routing and Switch Placement in EDA
Sep 30, 2026Dorian Gailhard, Ugo Lecerf, Enzo Tartaglione +2Electronic Design Automation Chip Design
LTCI, Télécom Paris, Institut Polytechnique de Paris, France · Arteris IP
Massively Parallel Reinforcement Learning with a Chaotic Reconfigurable Clockless Chip
Sep 28, 2026Eric Oliveira-Gomes, Damien RontaniChip Design Chaos
CentraleSup´elec and Universit´e de Lorraine, LMOPS UR4423 Laboratory, Metz F-57070, France
Long-Horizon Analog Design Bench: Benchmarking Agents on Hours-Long Analog and Mixed-Signal Circuit Design Tasks
Sep 27, 2026Analog Design Bench TeamAnalog Design Analog
Self-Replicating Neural Cellular Automata: Quantifying Emergent Phenotypic and Genotypic Diversity in an OpenEnded Substrate
Sep 17, 2026Sanyam Jain, Felix Simon Reimers, Stefano NicheleNeural Cellular Automata Self-Organization
Department of Computer Science and Communication, Østfold University of Applied Sciences, B R A veien 4, 1757 Halden, Norway · Department of Computer Science, Oslo Metropolitan University, Pilestredet 35, 0166 Oslo, Norway
From Ideas to Actions: A Public-Data Decision-Support Toolchain Across the Venture Lifecycle
Sep 14, 2026Lei QuFinancial Strategy Research Software Engineering Decision Support
Shanghai Xing Yun Zhi Li AI Institute · Shanghai Xing Yun Zhi Li AI Institute, China · Shanghai Xing Yun Zhi Li AI Institute, Shanghai, China
Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs
Sep 3, 2026Yujie Zhang, Huiying Lan, Ehsan Aghapour +5Chip Design Inference Latency
School of Computing, National University of Singapore, Singapore · Parallel Computer Systems, the University of Amsterdam, 1098 XH Amsterdam, The Netherlands · Information Technology Department, Black Sesame Technologies, San Jose, CA 95131, USA
RACE-AIMC: Selective Inference for Heterogeneous Analog In-Memory Accelerators at the Edge
Sep 2, 2026Osama Yousuf, Martin Lueker-BodenIn-Memory Computing Neural Network Inference
WD Research San Jose, CA, USA
Forward and Inverse Virtual Metrology for Phototransistor Gain: A Hierarchical, Uncertainty-Aware Approach for Small Production Datasets
Aug 12, 2026Mahshid Amirabgir, Lorenza Ferrario, Paolo Conci +2Semiconductor Manufacturing Chip Design
Micro Nano Facility (MNF), Center for Sensors and Devices, Fondazione Bruno Kessler (FBK), Via Sommarive 18, Povo (Trento), 38123, Italy. · Microfab Solutions, Via Sommarive 18, Povo (Trento), 38123, Italy. · Department of Civil and Environmental Engineering (DICA), Politecnico di Milano, Piazza Leonardo da Vinci 32, Milan, 20133, Italy. +1
ICM Out! Better Tournament Strategy from Computed Continuations, vs. Solvers and LLMs
Aug 10, 2026Boning Li, Longbo HuangPoker Competition
IIIS, Tsinghua University.
Hardware Design and Security in the Era of Chiplets and LLMs
Aug 5, 2026Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz +1Chip Design Semiconductor Manufacturing
NYU Abu Dhabi · Texas A&M University · NYU Tandon School of Engineering
SpreadMark: Robust Image Watermarking via Spread-Spectrum Embedding
Aug 4, 2026Wei Song, Yuxin Cao, Zhenchang Xing +4Watermarks Deepfake Detection
University of New South Wales, Australia · National University of Singapore, Singapore · CSIRO’s Data61, Australia
EDATracer: An Agentic Framework for Large-Scale EDA Artifact Analysis
Aug 2, 2026Phat Tieu, Sayanti Jana, Matthew DeLorenzo +5Electronic Design Automation Chip Design
Texas A&M University, Department of Electrical and Computer Engineering College Station, Texas 77840, USA
Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair
Jul 30, 2026Ha Trung TranFormal Verification High-Level Synthesis
Independent Researcher · Seattle, WA, USA
The SpiNNaker2 chip: a many-core platform for flexible and scalable brain-inspired computing
Jul 27, 2026Stefan Scholze, Johannes Partzsch, Sebastian Höppner +27Neuromorphic Computing Chip Design
Chair of Highly-Parallel VLSI-Systems and Neuro-Microelectronics, Technische Universität Dresden, Germany · Centre for Tactile Internet with Human-in-the-loop (CeTI) · Advanced Processor Technologies Group, Department of Computer Science, University of Manchester, UK +2
CHiPS: Character Histograms and Positional Signals for Lightweight Authorship Attribution in Romanian Texts
Jul 24, 2026Sanda-Maria Avram, George C. ŢurcaşAuthorship Handwritten Text Recognition
Department of Computer Science, Faculty of Mathematics and Computer Science, Babeș-Bolyai University, Cluj-Napoca, Romania · Department of Mathematics, Faculty of Mathematics and Computer Science, Babeș-Bolyai University, Cluj-Napoca, Romania
LLM for EDA in Front-End Design: Challenges and Opportunities
Jul 10, 2026Kangwei Xu, Bing Li, Ulf SchlichtmannElectronic Design Automation High-Level Synthesis
Chair of Electronic Design Automation, Technical University of Munich (TUM), Munich, Germany · Resource-Efficient AI Group, Technical University of Ilmenau, Ilmenau, Germany
Silicon Sampling via Cross-Survey Transfer
Jul 3, 2026Chan-Tung Ku, Chan Hsu, Pei-Cing Huang +3Survey Democracy
Department of Information Management National Sun Yat-sen University Kaohsiung, Taiwan · Institute of Political Science National Sun Yat-sen University Kaohsiung, Taiwan · Graduate Institute of Library and Information Science National Chung Hsing University Taichung, Taiwan
Agentic Hardware Design as Repository-Level Code Evolution
Jun 26, 2026Cunxi Yu, Chenhui Deng, Nathaniel Pinckney +1Self-Evolving Agents Repository-Level Code Understanding
NVIDIA Research
Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
Jun 21, 2026Poornima Kumaresan, Santhosh SivasubramaniNeuromorphic Computing Reram Crossbar
Intrinsic Lab, Centre for Sensors, Instrumentation and Cyber-Physical System Engineering (SeNSE), Indian Institute of Technology Delhi, New Delhi 110016, India
Multi-Level Resistive Synapses for On-Chip Neural Networks: A Physics-Based Design of a Memristive Crossbar Fabric with Quasi-Continuous Conductance States
Jun 21, 2026David Alejandro Trejo PizzoReram Crossbar Neuromorphic Computing
Independent researcher.
Failure Analysis in Transition: An Industry Survey of Challenges, Priorities, and Standardization Needs in Advanced Packaging and Heterogeneous Integration
Jun 20, 2026Himanandhan Reddy Kottur, Nusra Akter Takia, Mahamudul Hassan Fuad +3Semiconductor Manufacturing Chip Design
Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA · Florida Semiconductor Engine, Kissimmee, FL, USA
Library-Aware Doubles and Iterative Repair for Large Language Model-Generated Unit Tests in OpenSIL Firmware
Jun 18, 2026Ma Toan Bach, Yuchi Zheng, Haingo Razafindranto +4Test Generation Chip Design
School of Software Design and Data Science Seneca Polytechnic Canada · Advanced Micro Devices Canada
DART: A design-aware microfluidic chip paradigm for real-time live-cell image analysis
Jun 16, 2026Johannes Seiffarth, Matthias Pesch, Lukas Scholtes +3Microscopy Fluid Controls
Institute for Bio- and Geosciences, IBG-1: Biotechnology, Forschungszentrum Jülich, Jülich, Germany · Computational Systems Biotechnology (AVT.CSB), RWTH Aachen University, Aachen, Germany · Institute for Advanced Simulation, IAS-8: Data Analytics and Machine Learning, Forschungszentrum Jülich, Jülich, Germany
LLM4RTL: Tool-Assisted LLM for RTL Generation
Jun 13, 2026Jing Jin, Robert Chu, Ning Yan +1High-Level Synthesis Register Transfer Level
UC Riverside · Riverside, CA, USA · Futurewei +1
SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC
Jun 8, 2026Sonu Kumar, Akash Sankhe, Mukul Lokhande +1Risc-V Neural Network Inference
Centre for Advanced Electronics · Dept. of Electrical Engineering
Order Matters: Unveiling the Hidden Impact of Macro Placement Sequences via Proxy-Guided LLM Evolution
Jun 8, 2026Shibing Mo, Jing Liu, Jianchu Xu +1Chip Design Layouts
the School of Artifcial Intelligence, Xidian University · the Guangzhou Institute of Technology, Xidian University.
Programmable Silicon Retina on Pixel Processor Array
Jun 6, 2026Maciej Lewandowski, Prince Philip, Alexandre Marcireau +3Saliency Vision Sensors
Department of Electrical and Electronic Engineering University of Manchester, UK · Department of Electronic Systems Engineering, Indian Institute of Science, Bangalore, India · Department of Computer Science University of Manchester, UK
ITP-STDP: A Hardware-Efficient Intrinsic-Timing Power-of-Two Synaptic Learning Engine for On-Chip SNNs
Jun 4, 2026Haihang Xia, Xinyu Zhao, Xuecheng Wang +5Spiking Neural Networks Field-Programmable Gate Arrays
School of Electrical and Electronic Engineering, The University of Shefﬁeld, S1 3JD Shefﬁeld, U.K. · Donghai Laboratory, Zhoushan 316021, China · Engineering Research Center of Oceanic Sensing Technologyand Equipment, Ministry of Education, Zhoushan 316021, China +1
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
Jun 4, 2026Mohammad Akyash, Nowfel Mashnoor, Kimia Azar +1Hierarchical Register Transfer Level Generation Register Transfer Level
Department of Electrical and Computer Engineering (ECE), University of Central Florida, Orlando, FL 32816, USA
Operator Fusion for LLM Inference on the Tensix Architecture
Jun 3, 2026Qingbo Wu, Ke Li, Wenzhu Wang +3Transformer Architectures LLM Inference Optimization
KylinSoft Co., Ltd, Tianjin, China · openKylin Community, Tianjin, China · College of Computer Science and Technology, National University of Defense Technology, Changsha, China
Feasibility of Time-Domain DNN-Based Speech Enhancement on Embedded FPGA for Hearing Aid
Jun 2, 2026Feyisayo Olalere, Umut Altin, Kiki van der Heijden +1Speech Enhancement Speech Separation
Radboud University, Donders Institute for Brain, Cognition, and Behaviour, The Netherlands · Mortimer B. Zuckerman Mind, Brain, Behavior Institute, Columbia University, USA.
EASE Configuration Facilitates A Reproducible Science of LLM Social Simulations
May 28, 2026Sneheel Sarangi, Maximilian Puelma Touzel, Aurélien Bück-Kaeffer +3Scaling Improve Social Simulation Multi-Agent Simulations
McGill University · Mila - Quebec Artificial Intelligence Institute · Université de Montréal +1
Reinforcement learning for ion shuttling on trapped-ion quantum computers
May 21, 2026Maximilian Schier, Lea Richtmann, Christian Staufenbiel +4Quantum Processor Quantum Circuits
Institute for Information Processing (tnt), L3S, Leibniz University Hannover, Germany · Institute for Gravitational Physics, Leibniz University Hannover, Germany · QUDORA Technologies GmbH +3
Mapping Tomato Cropping Systems in California Using AlphaEarth Geospatial Embeddings and Deep Learning Analysis
May 20, 2026Mohammadreza Narimani, Alireza Pourreza, Parastoo FarajpoorAgricultural Monitoring Deep Learning
Department of Biological and Agricultural Engineering, University of California, Davis, Davis, CA, 95616, USA
FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction
May 19, 2026Haoyi Zhang, Kairong Guo, Bojie Zhang +2Communication Topologies Chip Design
School of Integrated Circuits, Peking University, Beijing, China · PicoHeart, Beijing, China
Memory-Guided Tree Search with Cross-Branch Knowledge Transfer for LLM Solver Synthesis
May 17, 2026Fatemeh Haji, Javier Delarosa Quiros, Peyman NajafiradFunctional Code Solvers Tree Search
Secure AI and Autonomy Lab · The University of Texas at San Antonio
Scalable neuromorphic computing from autonomous spiking dynamics in a clockless reconfigurable chip
May 15, 2026Eric Oliveira Gomes, Damien RontaniNeuromorphic Computing Time-To-First-Spike
LMOPS UR4423 Laboratory, CentraleSup´elec and Universit´e de Lorraine, Metz F-57070, France
Rule2DRC: Benchmarking LLM Agents for DRC Script Synthesis with Execution-Guided Test Generation
May 15, 2026Jinuk Kim, Junsoo Byun, Donghwi Hwang +2Test Generation Chip Design
Department of Computer Science and Engineering, Seoul National University · Neural Processing Research Center · Samsung Electronics Co., Ltd.
Bridging Silicon and the Hippocampus: Algebro-Deterministic Memory "VaCoAl" as a Substrate for Vector-HaSH and TEM
May 15, 2026Hiroyuki Chuma, Kanji Otsuka, Yoichi SatoDense Associative Memory Human Visual Cortex
Institute of Innovation Research, Hitotsubashi University, Kunitachi, Tokyo 186-8603, Japan · Meisei University, Hino, Tokyo, Japan · Shuhari System, Tokyo, Japan
Embodied Neurocomputation: A Framework for Interfacing Biological Neural Cultures with Scaled Task-Driven Validation
May 13, 2026Johnson Zhou, Daniel Tanneberg, Forough Habibollahi +12Neuromorphic Computing Neuroevolution
Cortical Labs, Australia · Honda Research Institute Europe, Germany
Metal-Sci: A Scientific Compute Benchmark for Evolutionary LLM Kernel Search on Apple Silicon
May 10, 2026Víctor GallegoShape-Memory Alloy Chip Design
Komorebi AI Technologies, Madrid, Spain
Variational Matrix-Learning Fourier Networks for Parametric Multiphysics Surrogates
May 4, 2026Xinyu Li, Jianhua Zhang, Liang ChenParametric Physics-Informed Neural Network Finite Element Method
School of Microelectronics, Shanghai University, Shanghai 201800, China
DiagramNet: An End-to-End Recognition Framework and Dataset for Non-Standard System-Level Diagrams
May 2, 2026Jincheng Lou, Ruohan Xu, Jiapeng Li +6Diagrams Table Reasoning Datasets
School of IC, Peking University, Beijing, China · College of Artificial Intelligence, Xi’an Jiaotong University, Xi’an, China · Department of Precision Instruments, Tsinghua University, Beijing, China +4
Silicon Showdown: Performance, Efficiency, and Ecosystem Barriers in Consumer-Grade LLM Inference
May 1, 2026Abdurrahman Javat, Allan KazakovLLM Inference Optimization Chip Design
Bahcesehir University, Istanbul, Türkiye
The $\textit{Silicon Society}$ Cookbook: Design Space of LLM-based Social Simulations
Apr 30, 2026Aurélien Bück-Kaeffer, Sneheel Sarangi, Maximilian Puelma Touzel +3Scaling Improve Social Simulation Chip Design
McGill University · Mila - Quebec Artificial Intelligence Institute · Ubisoft La Forge +2
Autoformalizing Memory Specifications with Agents
Apr 30, 2026Jan Ole Ernst, Dmitri Michelangelo Saberi, Derek Christ +6Chip Design Autoformalization
Normal Computing · Fraunhofer Institute for Experimental Software Engineering (IESE), Kaiserslautern, Germany · University of Würzburg, Germany
How Can Reinforcement Learning Achieve Expert-level Placement?
Apr 28, 2026Ruo-Tong Chen, Ke Xue, Chengrui Gao +7Offline Reinforcement Learning Layouts
State Key Laboratory of Novel Software Technology, Nanjing University, China · School of Artificial Intelligence, Nanjing University, China · Huawei Noah’s Ark Lab, China
The Collapse of Heterogeneity in Silicon Philosophers
Apr 26, 2026Yuanming Shi, Andreas HauptCollapse Heterogeneity
Adobe Inc., San Jose, California, USA · Stanford University, Departments of Economics and Computer Science, Stanford, California, USA
Kernel Contracts: A Specification Language for ML Kernel Correctness Across Heterogeneous Silicon
Apr 23, 2026Cooper VeitContracts Kernel Method
Ashiba Research
WarPGNN: A Parametric Thermal Warpage Analysis Framework with Physics-aware Graph Neural Network
Mar 19, 2026Haotian Lu, Jincong Lu, Sachin Sachdeva +1Graph Neural Networks Chip Design
Department of Electrical and Computer Engineering · University of California, Riverside · Riverside, CA, USA
Hybrid Event Frame Sensors: Modeling, Calibration, and Simulation
Nov 22, 2025Yunfan Lu, Nico Messikommer, Xiaogang Xu +5Vision Sensors Chip Design
1AI Thrust, HKUST(GZ) · RPG, University of Zurich · CUHK +1
Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design
Nov 6, 2023James T. MeechHigh-Level Synthesis Large Language Model Generation
University of Cambridge

Sep 30, 2026, cs.LGJ/K move · Enter open · S save

Validity-Preserving Hierarchical RL for Joint Routing and Switch Placement in EDA

Dorian Gailhard, Ugo Lecerf, Enzo Tartaglione, Donatello Conte+1

LTCI, Télécom Paris, Institut Polytechnique de Paris, France · Arteris IP

Electronic Design Automation Chip Design Hierarchical Reinforcement Learning Classical Planning Switch

Open paper AskPDF arXiv

Routing and switch placement are fundamental combinatorial optimization problems in chip design, requiring the joint optimization of routing topology and physical placement under strict structural, geometric and logical constraints. Existing approaches typically rely on carefully engineered heuristics that incorporate strong problem-specific biases to navigate the enormous space of possible designs. In this work, we introduce a hierarchical reinforcement learning framework for joint routing and switch placement at the level of logical communication routes. Starting from a minimal routing graph, our method progressively constructs increasingly expressive solutions through three coupled operations: switch expansion, switch placement, and route refinement. These operations preserve routing validity by construction, restricting exploration to feasible configurations where every communicating initiator-target pair has one assigned loop-free route. We explore the induced solution space using Gumbel Monte Carlo Tree Search, showing that neural-guided search substantially improves solution quality over non-learning optimization methods. Furthermore, pretraining across floorplans provides a strong initialization for fine-tuning on unseen instances.

Momentum

Related topics

Latest papers 52