LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation
Authors: Shu Gu, Matthew Youngman, Yuqin Zhao, Cristian Sestito, Ali Siddique, Ramesh Krishnamurthy, Danial Chitnis, Themis Prodromakis
Organizations: Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, U.K. · Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, U.K.
Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates large language model (LLM) orchestration from deterministic FPGA implementation and evaluation. Across sixteen designs and seven LLMs, a single-iteration study compares three agent control granularities - expert-written recipes, direct EDA operations and LLM-constructed procedures - to ask how much control an agent needs per attempt. Functional-pass rates are 98.2%, 71.4% and 17.9%, respectively; yet direct operations give slightly larger 3.4% median Fmax gains when passing, versus 3.2% for recipes. This exposes a trade-off between execution reliability and timing improvement. Informed by this trade-off, a multi-iteration study fixes the action tier at expert recipes to ask how repeated attempts are best organised, comparing a fitted deterministic heuristic with sequential LLM reasoning, branching exploration and knowledge base-guided exploration within 12 checkpoints per run. Branching raises mean maximum-frequency improvement from 10.5% (sequential) to 16.0%, and the knowledge base to 20.3%, improving 15 of 16 designs. Characterisation across 2,421 recipe attempts profiled their gain and validation rates, showing hard-block re-placement gives the largest cumulative mean gain at 41.4MHz.
Figures & tables
Work
Target / Input
Designs
Timing-feedback loop
Physical modification
Knowledge reuse
Search
Control-level study
InTime (2015) [ 9 ]
FPGA / RTL
6
✓
✓F
✓
Parallel batches
NR
DATuner (2017) [ 2 ]
FPGA / RTL
15 (10+5)
✓
✓F
✓
Adaptive batches
NR
LAMDA (2019) [ 10 ]
FPGA / RTL
5
✓E
✓F,E
✓
Multi-stage batches
NR
Nexus (2025) [ 21 ]
FPGA / RTL + constraints
14
✓
✓F
NR
Sequential refinement
NR
ORFS-agent (2025) [ 22 ]
ASIC / RTL + PDK
3 (2 nodes)
✓
✓F
✓
Parallel batches
NR
FluxEDA (2026) [ 23 ]
ASIC / routed design
1 (ECO case)
✓
✓D
✓
Sequential + rollback
NR
TABLE I: Selected learning-based approaches to backend timing and physical optimisation. Groups, from top: ML-based, LLM-based, and this work (shaded). Entries refer to the reported experiments.
Fig. 1: Checkpoint-based FPGA optimisation framework. Design evidence informs the choice of an expert optimisation recipe, direct EDA operations or a constructed procedure. The backend executes proposed modifications and evaluates checkpoints, only retaining validated candidates that improve Fmax .
Fig. 2: Illustrated example of sequential and branching optimisation patterns with retained checkpoints. An invalid attempt leaves its parent available, and branching allows alternative changes to start from the same checkpoint. The run history records applied changes and measured outcomes. Numerical values illustrate the workflow rather than experimental results.
Recipe
Function
fanout †
Splits timing-critical high-fanout nets by a factor of two to eight to reduce loading and routing delay.
auto_pblock
Defines a region from critical-path spread and fabric resources, then unplaces and re-implements the design inside.
net_swap
Targets problematic critical connections to reduce routing-related delay.
phys_opt
Runs Vivado physical optimisation after placement and routing, including replication, cell resizing and register movement.
lut_cone †
Merges LUT-dominated critical logic cones to reduce logic depth and path delay.
retime
Moves registers across combinational logic to reduce delay between sequential stages.
TABLE II: Expert optimisation recipes. All use Vivado; † additionally uses RapidWright for netlist modification.
Fig. 3: Analysis prompt for a recipe-selection decision. The design state, diagnosis, and available agent control interfaces – which change depending on which control level is available to the agent – are injected ( purple ), while the underlying template remains ( black ). A typical agent response is shown ( green ), ending in the ranked candidate list and the selected action.
Fig. 4: Example knowledge base recipe description, allowing the agent to reason about a recipe’s use case from generalised, non-benchmark-specific past information.
Fig. 5: Reliability and timing improvement across 16 designs and seven LLMs (112 trials per condition). (a) End-to-end functional-pass rates, with passing and total trial counts. (b) Percentage Fmax improvement relative to each trial’s starting checkpoint, for functional-pass trials only. Points show individual trials with horizontal jitter for visibility. Boxes span the interquartile range; whiskers extend to the most extreme observations within 1.5 times that range. Labelled lines mark medians. Zero and negative improvements are retained.
Fig. 6: Progression from proposal generation to timing improvement for (a) Direct EDA operations and (b) Constructed procedures. Each row represents 16 trials for one LLM. Percentages are calculated over all 16 trials, with each stage retaining only trials that satisfy all preceding stages. The final stage requires a functional pass and ΔFmax>0 .
Fig. 7: Design–model timing outcomes under (a) Expert optimisation recipes and (b) Direct EDA operations. Each numeric cell shows percentage Fmax improvement relative to the starting checkpoint for one functional-pass trial; × denotes no functional pass. Initial Fmax gives the starting frequency in MHz. Designs are ordered by increasing initial Fmax ; both panels use the same design and model ordering and a common colour scale. Row pass percentages are calculated across seven models; column pass percentages are calculated across sixteen designs.
Circuit / model
Output
ΔFmax
WNS
Logic
Route
Limiting-path structure
(MHz)
(ns)
(ns)
(ns)
LogicNets / DeepSeek v4 Flash
Selected recipe
+9.5
−0.921
0.514
1.887
LUT / multiplexer path
30.8k LUTs, 1.7k FFs,
Best recorded recipe
+98.0
−0.494
0.509
1.467
LUT / multiplexer path
0 DSPs, 0 BRAMs
Direct operations
+117.0
−0.421
0.562
1.340
LUT / multiplexer path
FINN RadioML / GPT-5.6 Sol
Selected recipe
+9.1
−1.801
1.135
2.198
12-level carry/LUT path
73.6k LUTs, 45.8k FFs,
Best recorded recipe
+54.4
−1.347
1.155
1.566
12-level carry/LUT path
TABLE III: Physical case studies. Selected and Best denote the LLM-selected recipe and best recorded recipe from the same starting checkpoint; Direct denotes direct operations. Delays describe each output’s worst setup path. Resources describe the input.
Fig. 8: Best functional-pass Fmax improvement per benchmark for (a) the deterministic fitted heuristic and the LLM-based levels (b) sequential reasoning, (c) branching exploration and (d) knowledge base-guided exploration, each with Claude Sonnet 5, Gemini 3.6 Flash and GPT-5.6 Luna (best of three repeats).
TABLE IV: Implementation results for three designs, comparing the input checkpoint with the ablation levels.
Fig. 9: Effectiveness of the expert recipes across the multi-iteration study. (a) Share of each ablation level’s recipe attempts spent on each recipe. (b) Each recipe’s mean Fmax improvement per attempt, measured from the starting DCPs, and the share of its attempts passing physical validation.
Fig. 10: Cost assessment across multi-iteration runs, (a) language-model expense against Fmax improvement for every model-driven run, (b) phase time decomposed by pipeline stage beside the elapsed wall time.
Fig. 11: Summary of both studies: best functional-pass Fmax improvement per benchmark. (a) Single-iteration study: best of seven LLMs, one trial each, under expert recipes and direct EDA operations. (b) Multi-iteration study: the deterministic fitted heuristic (one run) and the LLM-based levels (best of three LLMs over five runs, three of them GPT-5.6 Luna repeats). (c) The best result per design, with the method, LLM and recipe sequence that achieved it.
Can large language models generate not just correct, but fast hardware? This paper investigates the question in financial FPGA design, where 5-10 nanoseconds of latency determines competitive advantage and designs iterate continuously as protocols, strategies, and regulations evolve. FinHardBench, a benchmark of 33 financial computing tasks, is presented together with three experiments that mirror the real-world FPGA iteration cycle: generating new modules from specifications, tuning system-level configurations across a 6-stage trading pipeline, and adapting existing modules to specification changes. Evaluation of six LLMs on 1530+ experiment rounds yields three findings: (1) models achieve 19-61% functional correctness with timing degradation up to 13.7× on specific tasks; (2) in system-level design space exploration, top LLMs converge to the optimal configuration with higher reliability than random search, simulated annealing, and Bayesian optimization baselines (5/5 seeds vs. 0-4/5 at the same 24-round budget); (3) strategy-level specification changes remain unsolved for most models. Across the six models, generation and DSE rankings overlap moderately: the strongest code generator is not the fastest architecture optimizer, and the weakest code generator (MiniMax M2.7) still reaches the system optimum on 4 of 5 seeds. On the tasks in FinHardBench, difficulty tracks training data pattern availability more closely than abstraction level. FinHardBench is released as an open-source benchmark.
Weimin Fu, Hejia Zhang, Minghao Shao +6
Lehigh University · University of California, San Diego · NYU Tandon School of Engineering +1
Recent advances in large language models (LLMs) have led to the emergence of coding agents capable of performing complex engineering tasks, including register-transfer level (RTL) design and optimization. Existing RTL benchmarks mainly evaluate functional correctness and performance, power, and area (PPA) of the generated RTL designs, leaving agents' ability for timing closure under-evaluated. We propose TicTacBench, a benchmark specifically designed to evaluate coding agents' capabilities for RTL-level timing closure under post-place-and-route (post-PnR) evaluation. TicTacBench contains 30 diverse tasks, each provided with a suboptimal RTL design, realistic timing constraints, functional equivalence verification, and timing reports. With over 300 runs of coding agents driven by 8 frontier LLMs, we find that even the best agent can only close 53.3% of tasks with 7.18% area-delay product (ADP) degradation and 8.83% energy-delay-squared product (EDDP) improvement on average. We identify common failure categories that explain why agents fail to close timing. Then we propose TicTacSkill, a new method that guides agents to follow standard timing-closure procedures and improves the Timing Closure Rate by 9%. These results suggest that while coding agents have made significant progress in RTL design, their timing-closure capability still has substantial room for improvement.
Bowei Wang, Zhigang Fang, Zhijie Yang +3
Computer Department, National University of Defense Technology, Changsha, China · Defense Innovation Institute, Academy of Military Science, Beijing, China · Intelligent Microelectronics Center, Qiyuan Lab, Beijing, China
Early, tool-free prediction of post-synthesis timing remains a key obstacle to rapid RTL iteration. We introduce TimingLLM, a two-stage retrieval-augmented LLM pipeline that estimates worst negative slack (WNS) and total negative slack (TNS) directly from Verilog. Stage 1 is a fine-tuned LLM that acts as a compact post-synthesis timing oracle, producing path-level arrivals/required times that are summarized into lightweight structural-timing cues (e.g., bag-of-gates counts, critical-path depth, gate-type patterns). Stage 2 is an LLM-based regressor that predicts WNS/TNS and applies a learned diagonal steering vector at the last transformer block, computed from the k nearest timing-labeled modules in a disjoint retrieval bank. On VerilogEval, TimingLLM attains R_WNS = 0.91 (MAPE 12%) and R_TNS=0.97 (MAPE 16%) while running 1.3-1.6 times faster than prior methods. Training uses a new 60k-module Verilog corpus with synthesis reports, which we will release. After training once, TimingLLM can be adapted to new technology libraries and PVT corners by refitting only a small regression head on 1000 labeled modules per setting, consistently outperforming state-of-the-art baselines.
Armin Abdollahi, Negin Ashrafi, Mehdi Kamal +1
University of Southern California Los Angeles, CA, USA