LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation

Shu Gu; Matthew Youngman; Yuqin Zhao; Cristian Sestito; Ali Siddique; Ramesh Krishnamurthy; Danial Chitnis; Themis Prodromakis

cs.AIOct 12, 2026

LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation

Authors: Shu Gu, Matthew Youngman, Yuqin Zhao, Cristian Sestito, Ali Siddique, Ramesh Krishnamurthy, Danial Chitnis, Themis Prodromakis

Organizations: Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, U.K. · Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, U.K.

Abstract

Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates large language model (LLM) orchestration from deterministic FPGA implementation and evaluation. Across sixteen designs and seven LLMs, a single-iteration study compares three agent control granularities - expert-written recipes, direct EDA operations and LLM-constructed procedures - to ask how much control an agent needs per attempt. Functional-pass rates are 98.2%, 71.4% and 17.9%, respectively; yet direct operations give slightly larger 3.4% median Fmax gains when passing, versus 3.2% for recipes. This exposes a trade-off between execution reliability and timing improvement. Informed by this trade-off, a multi-iteration study fixes the action tier at expert recipes to ask how repeated attempts are best organised, comparing a fitted deterministic heuristic with sequential LLM reasoning, branching exploration and knowledge base-guided exploration within 12 checkpoints per run. Branching raises mean maximum-frequency improvement from 10.5% (sequential) to 16.0%, and the knowledge base to 20.3%, improving 15 of 16 designs. Characterisation across 2,421 recipe attempts profiled their gain and validation rates, showing hard-block re-placement gives the largest cumulative mean gain at 41.4MHz.

Figures & tables

Work	Target / Input	Designs	Timing-feedback loop	Physical modification	Knowledge reuse	Search	Control-level study
InTime (2015) [ 9 ]	FPGA / RTL	6	$\checkmark$	$\checkmark^{\mathrm{F}}$	$\checkmark$	Parallel batches	NR
DATuner (2017) [ 2 ]	FPGA / RTL	15 (10+5)	$\checkmark$	$\checkmark^{\mathrm{F}}$	$\checkmark$	Adaptive batches	NR
LAMDA (2019) [ 10 ]	FPGA / RTL	5	$\checkmark^{\mathrm{E}}$	$\checkmark^{\mathrm{F,E}}$	$\checkmark$	Multi-stage batches	NR
Nexus (2025) [ 21 ]	FPGA / RTL + constraints	14	$\checkmark$	$\checkmark^{\mathrm{F}}$	NR	Sequential refinement	NR
ORFS-agent (2025) [ 22 ]	ASIC / RTL + PDK	3 (2 nodes)	$\checkmark$	$\checkmark^{\mathrm{F}}$	$\checkmark$	Parallel batches	NR
FluxEDA (2026) [ 23 ]	ASIC / routed design	1 (ECO case)	$\checkmark$	$\checkmark^{\mathrm{D}}$	$\checkmark$	Sequential + rollback	NR

TABLE I: Selected learning-based approaches to backend timing and physical optimisation. Groups, from top: ML-based, LLM-based, and this work (shaded). Entries refer to the reported experiments.

Fig. 1: Checkpoint-based FPGA optimisation framework. Design evidence informs the choice of an expert optimisation recipe, direct EDA operations or a constructed procedure. The backend executes proposed modifications and evaluates checkpoints, only retaining validated candidates that improve $F_{\max}$ .

Fig. 2: Illustrated example of sequential and branching optimisation patterns with retained checkpoints. An invalid attempt leaves its parent available, and branching allows alternative changes to start from the same checkpoint. The run history records applied changes and measured outcomes. Numerical values illustrate the workflow rather than experimental results.

Recipe	Function
fanout †	Splits timing-critical high-fanout nets by a factor of two to eight to reduce loading and routing delay.
auto_pblock	Defines a region from critical-path spread and fabric resources, then unplaces and re-implements the design inside.
net_swap	Targets problematic critical connections to reduce routing-related delay.
phys_opt	Runs Vivado physical optimisation after placement and routing, including replication, cell resizing and register movement.
lut_cone †	Merges LUT-dominated critical logic cones to reduce logic depth and path delay.
retime	Moves registers across combinational logic to reduce delay between sequential stages.

TABLE II: Expert optimisation recipes. All use Vivado;

\dagger

additionally uses RapidWright for netlist modification.

Fig. 3: Analysis prompt for a recipe-selection decision. The design state, diagnosis, and available agent control interfaces – which change depending on which control level is available to the agent – are injected ( purple ), while the underlying template remains ( black ). A typical agent response is shown ( green ), ending in the ranked candidate list and the selected action.

Fig. 4: Example knowledge base recipe description, allowing the agent to reason about a recipe’s use case from generalised, non-benchmark-specific past information.

Fig. 5: Reliability and timing improvement across 16 designs and seven LLMs (112 trials per condition). (a) End-to-end functional-pass rates, with passing and total trial counts. (b) Percentage

F_{\max}

improvement relative to each trial’s starting checkpoint, for functional-pass trials only. Points show individual trials with horizontal jitter for visibility. Boxes span the interquartile range; whiskers extend to the most extreme observations within 1.5 times that range. Labelled lines mark medians. Zero and negative improvements are retained.

Fig. 6: Progression from proposal generation to timing improvement for (a) Direct EDA operations and (b) Constructed procedures. Each row represents 16 trials for one LLM. Percentages are calculated over all 16 trials, with each stage retaining only trials that satisfy all preceding stages. The final stage requires a functional pass and

\Delta F_{\max}>0

Fig. 7: Design–model timing outcomes under (a) Expert optimisation recipes and (b) Direct EDA operations. Each numeric cell shows percentage

F_{\max}

improvement relative to the starting checkpoint for one functional-pass trial;

\times

denotes no functional pass. Initial

F_{\max}

gives the starting frequency in MHz. Designs are ordered by increasing initial

F_{\max}

; both panels use the same design and model ordering and a common colour scale. Row pass percentages are calculated across seven models; column pass percentages are calculated across sixteen designs.

Circuit / model	Output	$\Delta F_{\max}$	WNS	Logic	Route	Limiting-path structure
		(MHz)	(ns)	(ns)	(ns)
LogicNets / DeepSeek v4 Flash	Selected recipe	+9.5	$-0.921$	0.514	1.887	LUT / multiplexer path
30.8k LUTs, 1.7k FFs,	Best recorded recipe	+98.0	$-0.494$	0.509	1.467	LUT / multiplexer path
0 DSPs, 0 BRAMs	Direct operations	+117.0	$-0.421$	0.562	1.340	LUT / multiplexer path
FINN RadioML / GPT-5.6 Sol	Selected recipe	+9.1	$-1.801$	1.135	2.198	12-level carry/LUT path
73.6k LUTs, 45.8k FFs,	Best recorded recipe	+54.4	$-1.347$	1.155	1.566	12-level carry/LUT path

TABLE III: Physical case studies. Selected and Best denote the LLM-selected recipe and best recorded recipe from the same starting checkpoint; Direct denotes direct operations. Delays describe each output’s worst setup path. Resources describe the input.

Fig. 8: Best functional-pass $F_{\max}$ improvement per benchmark for (a) the deterministic fitted heuristic and the LLM-based levels (b) sequential reasoning, (c) branching exploration and (d) knowledge base-guided exploration, each with Claude Sonnet 5, Gemini 3.6 Flash and GPT-5.6 Luna (best of three repeats).

Circuit / Model / Resources	Output	$\Delta F_{\max}$ (MHz)	WNS (ns)	Logic (ns)	Route (ns)	Limiting-path structure
BOOM SoC GPT-5.6 Luna 227k LUTs, 98k FFs, 61 DSPs, 161 BRAMs	Input checkpoint	–	$-19.162$	2.001	18.471	27-level LUT path to load queue
	Fitted heuristic	+43.9	$-9.283$	2.072	8.675	20-level LUT path to I-cache BRAM
	Sequential reasoning	+14.1	$-14.463$	1.220	15.001	16-level LUT path to register file
	Branching exploration	+41.4	$-9.583$	2.623	8.351	34-level LUT/multiplexer path to register file
	Knowledge base-guided	+49.3	$-8.685$	1.982	8.314	19-level LUT/carry path to register file
AMD mini-ISP v2 Gemini 3.6 Flash 3.2k LUTs, 4.5k FFs, 40 DSPs, 12 BRAMs	Input checkpoint	–	$-1.902$	0.394	2.711	5-level LUT path to line-buffer BRAM

TABLE IV: Implementation results for three designs, comparing the input checkpoint with the ablation levels.

Fig. 9: Effectiveness of the expert recipes across the multi-iteration study. (a) Share of each ablation level’s recipe attempts spent on each recipe. (b) Each recipe’s mean $F_{\max}$ improvement per attempt, measured from the starting DCPs, and the share of its attempts passing physical validation.

Fig. 10: Cost assessment across multi-iteration runs, (a) language-model expense against $F_{\max}$ improvement for every model-driven run, (b) phase time decomposed by pipeline stage beside the elapsed wall time.

Fig. 11: Summary of both studies: best functional-pass $F_{\max}$ improvement per benchmark. (a) Single-iteration study: best of seven LLMs, one trial each, under expert recipes and direct EDA operations. (b) Multi-iteration study: the deterministic fitted heuristic (one run) and the LLM-based levels (best of three LLMs over five runs, three of them GPT-5.6 Luna repeats). (c) The best result per design, with the method, LLM and recipe sequence that achieved it.

Figure 16

Electronic Design Automation

Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.

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Can large language models generate not just correct, but fast hardware? This paper investigates the question in financial FPGA design, where 5-10 nanoseconds of latency determines competitive advantage and designs iterate continuously as protocols, strategies, and regulations evolve. FinHardBench, a benchmark of 33 financial computing tasks, is presented together with three experiments that mirror the real-world FPGA iteration cycle: generating new modules from specifications, tuning system-level configurations across a 6-stage trading pipeline, and adapting existing modules to specification changes. Evaluation of six LLMs on 1530+ experiment rounds yields three findings: (1) models achieve 19-61% functional correctness with timing degradation up to 13.7

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Abstract

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