Spiking Neural Networks (SNNs) are promising for energy-efficient spatiotemporal pattern recognition at the edge, but efficient deployment and on-device adaptation require specialized hardware. In this work, we present an FPGA implementation of multilayer SNNs for spatiotemporal pattern classification, in which both inference and training take place on the same hardware. Our design adopts a temporal-forward-only training algorithm that avoids the memory and latency overhead associated with traditional Backpropagation Through Time (BPTT). A mixed-precision scheme balances training stability with resource efficiency, and architectural optimization maximizes hardware and memory utilization. We further identify and resolve hazards that arise when inference and learning share the same memory, including port conflicts between the forward and backward access patterns and read-after-write dependencies in floating-point potential accumulation. Experimental evaluations on MNIST and five multivariate time-series classification datasets demonstrate that, with fully on-chip training, our SNN model achieves accuracy comparable to SNN or LSTM trained with BPTT. Compared to CPU and GPU based implementations, our FPGA design delivers 2.5 to 6 times higher throughput while consuming an order of magnitude less energy per sample.
Figures & tables
Fig. 1: Neuron model of the multilayer SNN
Fig. 2: Architecture and data flow of the multilayer SNN FPGA implementation. The forward and backward passes read the same on-chip weight matrix in conflicting orders—row-major ( W ) versus column-major ( W⊤ )—motivating the partitioning and interleaving scheme.
Fig. 3: Weight matrix partition and shuffle
Fig. 4: Resolution of RAW hazard with buffer
Dataset
Input Dim
Length
Classes
Type
MNIST
784
1
10
Static
BasicMotions[20]
6
100
4
Temporal
Epilepsy[24]
3
207
4
Temporal
FingerMovements[25]
28
50
2
Temporal
Racket Sports[20]
6
30
4
Temporal
Japanese Vowels[21]
12
29
9
Temporal
TABLE I: Dataset Information
Impl.
Network
Synapses
Timesteps
FPGA
LUT
FF
DSP
BRAM
Acc.
HaSiST ∗ [27]
784-200-10
158,800
15
Virtex-6
37.84 per synapse
2.63 per synapse
–
–
97.5%
TripleBrain § [23]
784-256
200,704
200
Zynq-7045
16,584 †
33,168 †
32
131
95.10%
Ours
784-100-100-10
89,400
10
ZCU102
87,577
63,642
712
202
95.92%
∗ HaSiST trains a surrogate ANN and transfers weights to SNN for inference. DSP and BRAM are not reported.
§ TripleBrain use SOM-STDP and R-STDP. Resource reported as slices; TripleBrain uses a single-layer SNN with no multilayer gradient-based training.
† Converted from reported slices (Zynq-7000: 4 LUTs and 8 FFs per slice); upper-bound estimates.
TABLE II: MNIST Accuracy Comparison Among FPGA-based On-chip Learning Implementations
Spiking neural networks process information through discrete, time-dependent neural events, aiming for efficient computation and biologically inspired learning.