LOADBench: A Large Open Analog Dataset and Benchmark for Machine Learning in IC Design

M. Leibl; F. Azevedo; S. Uhlich; A. Bonetti; A. Venkitaraman; C. Hsieh; P. Pham; L. Servadei

cs.AIOct 15, 2026

LOADBench: A Large Open Analog Dataset and Benchmark for Machine Learning in IC Design

Authors: M. Leibl, F. Azevedo, S. Uhlich, A. Bonetti, A. Venkitaraman, C. Hsieh, P. Pham, L. Servadei,

Organizations: TUM / Chair of Electronic Design Automation · Instituto de Telecomunicações (IT) / IST-UL · SonyAI · TUM / Chair of DA ·

Abstract

Machine learning (ML) for analog IC design is constrained by limited open data and the absence of standardized evaluation: results reported in different papers are typically obtained on bespoke, often closed, datasets and with ad-hoc metrics, leaving comparisons across methods unreliable. We address both gaps with a large opensource dataset and a suite of standardized benchmarks. The dataset contains more than 100 operational amplifier (opamp) topologies (1-, 2-, and 3-stage) in the SkyWater130 PDK, each shipped with structural and functional annotations, topology-specific sizing constraints (symmetry and sizing rules), an Ngspice testbench, and a multi-objective NSGA-II sizing run producing around 103 Pareto-optimal and 106 intermediate sizing-performance pairs per topology. On top of this data we define six benchmark tasks with precise protocols: inverse sizing, topology selection, sub-circuit classification, structural circuit generation, Pareto-membership prediction, and multi-objective optimization. Thus, the data presented here constitutes the most comprehensive dataset for ML development in over four decades of analog IC design automation. The dataset, ground-truth annotations, and reference implementations of the metric-defining routines are released under an open license, enabling reproducible and directly comparable evaluation across heterogeneous analog design automation methods.

Figures & tables

Benchmark	# Top.	Sizings	Open tools	Struct.	Scope
AnalogGym ( Li et al., 2024 )	30	–	part.	no	any
AICircuit ( Mehradfar et al., 2024 ; Mehradfar et al., 2025 )	9	$3\!\times\!10^{5}$	no	no	any
AMSBench ( Shi et al., 2025 )	–	–	–	no	LLM
AnalogCoder ( Lai et al., 2024 )	24	–	–	no	LLM
Ours	$\mathbf{>100}$	$\mathbf{\sim 10^{8}}$	yes	yes	any

Table 1. Comparison of open analog IC design benchmarks. “Open tools” indicates a fully open-source workflow (PDK, simulator where applicable); “Struct.” indicates whether structural annotations are shipped. “Sizings” is the total number of sizing–performance pairs.

Metric	Symbol / name	Unit	Preferred a	HV ref.	Performance constraints
Area	Area	$\mu\mathrm{m}^{2}$	smaller ⋆	8000	$\mathrm{Area}\leq 8000$
Common-mode rejection ratio	CMRR	dB	larger	–	$\mathrm{CMRR}\geq 40$
Low-frequency (DC) gain	$\text{A}_{\mathrm{v,DC}}$	dB	larger ⋆	0	$\text{A}_{\mathrm{v,DC}}\geq 0$
Transit frequency	F t	Hz	larger ⋆	0	$\text{F\textsubscript{t}}\geq 1000$
Maximum input common-mode voltage	ICMR max	V	larger ⋆	1.0	$\text{ICMR\textsubscript{max}}\geq 1.0$
Minimum input common-mode voltage	ICMR min	V	smaller ⋆	1.1	$\text{ICMR\textsubscript{min}}\leq 1.1$

Table 2. Performances and constraints used during dataset generation. The Preferred column indicates whether larger or smaller values are preferred. The HV ref. column lists the reference value used for hypervolume computation in Sec. 3.4 ; units match the Unit column.

Figure 1. Example for recognized structural blocks.

Figure 2. Example for recognized functional blocks.

Figure 3. Benchmarked inverse sizing task.

Method	Query metrics	Train			Validation			Test
Method	Query metrics	Top-1	Top-3	MFHR	Top-1	Top-3	MFHR	Top-1	Top-3	MFHR
Random baseline	DC gain only	80.4%	95.4%	2.07	81.5%	94.3%	1.42	75.5%	92.5%	1.61
	DC gain + F t	53.2%	82.6%	3.62	57.3%	84.8%	2.18	56.3%	81.9%	2.43
	All active metrics	3.2%	8.5%	43.80	8.0%	23.6%	7.22	7.8%	22.9%	7.57
Learned embedding	DC gain only	86.4%	88.9%	1.37	92.1%	100.0%	1.08	91.9%	100.0%	1.14
	DC gain + F t	80.1%	94.9%	1.45	68.6%	99.0%	1.43	86.7%	92.6%	1.44

Table 3. Top-

k

topology selection accuracy and mean first-hit rank (MFHR) for different metric-query settings.

Figure 4. FCNN and loss for inverse sizing example.

	MAPE (%)	Std. (%)	Outl. (%)	Spec. (%)	$R^{2}$
DC Gain	1.90	5.61	0.20	46.48	0.94
F t	13.42	26.78	3.32	49.80	0.98
Power	8.03	13.68	2.54	52.34	0.99
Phase Margin	5.36	15.82	1.56	53.12	0.04
$\text{SR}_{\text{neg}}$	26.28	79.91	9.57	50.00	0.90
$\text{SR}_{\text{pos}}$	22.55	50.23	4.10	55.02	0.96

Table 4. Pooled inverse-sizing results for one-stage opamps. Each row reports per-performance MAPE, APE standard deviation, outlier rate, spec-satisfaction rate, and

R^{2}

Appendix figures & tables3 assets

Supplementary material from the paper’s appendix.

Appendix

Panel of Figure 5 — Figure 5. Two example opamp topologies from the dataset and interpolated 3D projections of the POF of opamp 5(b) .

	(a) 2-stage opamps														(b) 3-stage opamps
	Gain	F t	P	PM	SR -	SR +	V ${}_{\text{off}}$	CMRR	PSRR	$\text{ICMR}_{-}$	$\text{ICMR}_{+}$	$\text{V}_{\text{o+}}$	$\text{V}_{\text{o-}}$	Area	Gain	F t	P	PM	SR -	SR +	V ${}_{\text{off}}$	CMRR	PSRR	$\text{ICMR}_{-}$	$\text{ICMR}_{+}$	$\text{V}_{\text{o+}}$	$\text{V}_{\text{o-}}$	Area
MAPE (%)	3.68	10.26	6.00	6.36	22.25	14.04	40.15	6.00	8.74	5.99	6.14	4.36	0.99	3.47	51.68	96.33	10.92	74.32	37.82	37.51	169.96	21.85	71.29	17.69	22.87	81.43	12.19	4.35
Std. (%)	9.24	40.57	10.59	52.49	88.08	51.28	138.44	12.45	14.37	10.09	17.65	17.31	1.96	4.72	133.73	242.49	35.88	146.36	134.45	87.91	341.48	58.21	189.67	26.65	32.98	150.27	22.73	4.61
Outl. (%)	0.78	3.14	1.57	0.59	5.88	4.12	10.39	1.18	2.35	1.76	4.12	0.78	0.20	0.20	12.75	9.41	2.16	29.41	4.51	8.63	26.86	11.18	12.75	2.35	28.43	12.35	7.25	0.39
Spec. (%)	56.47	50.69	54.12	42.83	47.51	51.69	51.37	49.22	46.47	56.57	42.80	55.80	44.99	51.37	44.71	60.00	43.73	23.92	48.22	32.99	48.04	43.14	47.65	72.11	34.50	71.97	60.24	46.86
$R^{2}$	0.88	0.99	0.99	-2e3	0.99	0.99	-3.83	0.46	0.35	0.97	-0.31	0.94	0.98	0.98	-48.64	-25.55	0.96	-114.70	0.83	0.50	-213e3	-18.09	-99.89	-0.62	-1.85	-3.38	-5.76	0.84

Appendix

Table 5. Pooled inverse-sizing results. Metrics and performances as in table 4 .

Figure 6. UMAP visualization of the learned embedding space for queries using DC gain and F t .

Electronic Design Automation

Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.

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AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing

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Large Language Model-Guided Optimization Electronic Design Automation Analog Circuit Sizing Multi-Agent LLMs LLM Agent Planning

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Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled technologies. Although recent large language model (LLM)-based methods show promise in improving sample efficiency and interpretability, existing approaches often lack explicit circuit-topology understanding and are mainly evaluated on relatively simple analog building blocks. This paper presents a multi-agent LLM-based framework for complex analog circuit sizing. The proposed framework first analyzes the circuit topology and decomposes the netlist into functional blocks and substructures. It also extracts lightweight design knowledge for reuse. Based on the extracted topology and knowledge, a planner coordinates multiple role-specialized sizing agents to update design variables and achieve global performance specifications. This workflow mimics the collaborative process of an expert analog design team and provides a structured, interpretable, and simulation-driven optimization procedure. The framework was validated on eight circuits, with the largest design containing up to 55 transistors and 60 sizing variables. Notably, for the LDO benchmark, the proposed method achieved a 60% success rate with an average of 83 iterations, where classical optimizers failed to find feasible solutions. Further, ablation studies demonstrate that topology understanding, design-knowledge infusion, and agent specialization provide complementary benefits. The source code is available to support reproducibility.

Abstract

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