Injection of Space Radiation Errors on Low-power NVM using Generative Deep Learning

Eleonora Giudici; Antonio Miele; Luca Mottola

cs.AROct 19, 2026

Injection of Space Radiation Errors on Low-power NVM using Generative Deep Learning

Authors: Eleonora Giudici, Antonio Miele, Luca Mottola

Organizations: Politecnico di Milano Milan, Italy · RISE and Uppsala University Uppsala, Sweden

Abstract

We develop an error model for a Non-Volatile Memory (NVM) device that represents the effects of physical faults experienced in a CubeSat mission in Low Earth Orbit (LEO). The CubeSat carries an off-the-shelf low-power Ferroelectric RAM (FRAM) chip and runs repeated read/write tests according to a predefined pattern. We compare every memory snapshot received from the satellite with a reference bitmap to identify bit errors. We visually analyze erroneous values distributions in the memory snapshots and we understand that they are frequently distributed according to regular spatial patterns. We define a generative deep learning technique to automatically learn these spatial patterns and to synthetically generate additional error patterns mimicking the observed ones. The model is capable at producing memory errors for general application-level experimentation. Our preliminary validation indicates that when comparing the model output with the data we collect, 0.92 of the generated bit flips correspond to bit flips in the memory snapshots and the model captures 0.91 of the observed bit flips. A comparison of the spatial distribution of bit flips in 10,000 generated error patterns also provides a Wasserstein distance of 0.073, indicating that the two distributions differ by roughly 7% of the maximum possible displacement of their probability masses.

Figures & tables

NVM chip	Fujitsu FRAM MB85RS64V
Bit configuration	8,192 words × 8 bits
Endurance	$10^{12}$ cycles/byte
Retention	$>10$ years
Supply voltage (min–max)	3.3–5.5 V
Current draw (min–max)	10µA-1.5mA

Table 1. NVM chip specifications. The information is taken from the corresponding datasheets.

Panel of Figure 1 — Figure 1. Space vehicle and hardware architecture. The CubeSat hosts the OBC and PDM at the bottom, tasked with mission control and energy management. The slave $0$ hosts the MCU controlling the experiments and the three NVM chips we test.

Figure 2. Slave 0 device on the CubeSat with NVM array. An additional 14mm-think aluminum enclosure protects the experimental scaffold, in addition to the 10 mm aluminum shields between slave devices/OBC, and the outer aluminum alloy frame of the satellite.

Panel of Figure 3 — Figure 3. VAE architecture for the error model. We use the regular encoder-decoder architecture on the left for training the model with data we collect; then, we feed the sole decoder with random inputs, as shown on the right, and use that as a generator of error masks.

Figure 4. Bit error probability heatmap for the FRAM chip. The darker the color of each bit, the higher the observed frequency of bit flip; the X mark indicates a bit stuck at a fixed value due to a hard error.

Synthetic Anomaly Generation

Synthetic anomaly generation creates controlled abnormal examples to train, test, and evaluate detectors when real anomalies are scarce.

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Deep neural networks (DNNs) have achieved state-of-the-art performance across diverse domains. However, typical Von Neumann compute paradigms face severe memory bottlenecks. Emerging near-memory and compute-in-memory approaches alleviate this but incur significant peripheral overhead. Computational Random Access Memory (CRAM) based on MRAM enables in-situ logic without peripheral overhead, offering a dense, energy-efficient solution. However, probabilistic MRAM switching induces gate-level errors that limit the scalability and reliability of CRAM for accelerating DNN. Moreover, the large number of sequential MRAM writes severely constrains CRAM throughput. To address these challenges, we propose an error-resilient CRAM (CRAM-ER) architecture for scalable in-memory matrix-vector multiplications (MVMs). Our error-aware hardware-software co-design framework leverages a hybrid spintronic-CRAM + CMOS adder-tree architecture to mitigate the impact of device-level errors, demonstrating MVM functionality with high area and energy efficiency. We further develop an error-aware model fine-tuning and fine-grained error correction for enhanced error resilience. Evaluations of the CMOS+spintronic hybrid architecture on DNN benchmarks show near-lossless accuracy while reducing CRAM latency by up to 2 orders of magnitude, outperforming CPU/GPU+high-bandwidth DRAM in both energy efficiency and energy-delay product.

Abstract

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