From Natural Language to Real Schematics: An Automated Workflow for Power Electronics Schematic Synthesis

Bowen Su; Huan Chen; Jiahua Ying; Ran Ou; Weilong Chen; Li Xue; Kai Sun

cs.AIOct 28, 2026

From Natural Language to Real Schematics: An Automated Workflow for Power Electronics Schematic Synthesis

Authors: Bowen Su, Huan Chen, Jiahua Ying, Ran Ou, Weilong Chen, Li Xue, Kai Sun

Organizations: State Key Laboratory of Power System Operation and Control Department of Electrical Engineering Tsinghua University Beijing, China

Abstract

Designing power electronics converters traditionally requires intensive human expertise across topology sizing, commercial component selection, circuit simulation verification, and schematic drafting. While Large Language Models (LLMs) show promise in electronic design automation (EDA), applying standalone LLMs directly to board-level power electronics schematic synthesis suffers from severe engineering hallucinations, including inaccurate analytical sizing, fabricated or mismatched component part numbers, violated voltage derating margins, and broken topological connectivity. In this paper, we propose a Bounded Dual-Loop Automated Schematic Synthesis Framework that translates natural language specifications into verified, editable KiCad schematics and manufacturing deliverables. Our workflow integrates six stages across three functional columns: (1) requirement parsing and knowledge-driven power stage synthesis covering non-isolated (Buck, Boost) and isolated/resonant (Flyback, DAB, half-bridge LLC) topologies; (2) contract- and evidence-coordinated component selection grounded in distributor APIs and OEM datasheets, coupled with closed-loop ngspice transient verification and stress feedback; and (3) modular control hardware integration and multi-format deliverable generation featuring native KiCad netlist round-trip verification. End-to-end case studies on a 24-36V to 12V,2A Buck converter (29 positions, 83 verified terminals) and an isolated 48V to 24V, 0.5A, Dual-Active Bridge (DAB) converter (87 positions, 341 verified terminals), alongside comparative evaluations against a Vanilla LLM baseline, demonstrate that our framework improves component verification coverage from 22.2 to 98.6, nominal value consistency from 0 to 97.7, and SPICE simulation pass rates from 0 to 100.

Figures & tables

Figure 1: Application scenarios of power electronics

Figure 2: The proposed Bounded Dual-Loop Automated Schematic Synthesis Framework . The architecture is organized into three functional columns from left to right: (1) Input Specifications , (2) Iteration & Search Engine , and (3) Integration & Deliverables . Deep purple solid arrows denote the forward synthesis and integration pipeline, whereas coral-orange solid arrows highlight the diagnostic feedback pathways ( Refine Query , Re-design , Stress Feedback , and Resize L/C ) governed by Decision Nodes 1 and 2.

Decision Node	Failure / Unmet Condition	Return Target (Figure 2 Label)	Corrective Action Taken
Decision 1: Selection Adequate? (Inner Loop)	Insufficient candidates or category mismatch	Stage 3: Candidate Pool ( Refine Query )	Adjust search keywords; expand manufacturer scope or distributor API sources.
	Missing critical parameters in candidate records	Stage 3: Evidence Verification ( Refine Query )	Supplement datasheets; extract missing parameters; verify part identity and conditions.
	Candidate key ratings violate contract $\mathcal{K}_{i}$	Stage 3: Contract Matching ( Refine Query )	Search for alternative commercial models satisfying electrical/thermal constraints.
	Design parameters unachievable by real COTS parts	Stage 2: Circuit Synthesis ( Re-design )	Adjust permissible design parameters or physical configurations while keeping user specs fixed.
Decision 2: Targets & Stress Verified? (Outer Loop)	Output voltage or ripple violates target tolerances	Stage 2: Circuit Synthesis ( Resize L/C )	Retune passive $L/C$ values, reference modulation parameters, or structural configurations.
	Simulated stress elevates device rating requirements	Stage 3: Component Selection ( Stress Feedback )	Update contract $\mathcal{K}_{i}$ at affected positions with simulated stresses; trigger targeted re-selection.

Table 1: Diagnostic Routing Logic and Solid Feedback Pathways at Decision Nodes 1 and 2

Category	Configuration / Setting
Default Workflow Engine	Deterministic parsing & topology sizing + basic real-part selection
Default Simulation Scope	Externally modulated power stage and gate driver ( ucc27714 adapter)
Basic Stress-Feedback Loop	Single-pass simulation-stress-informed component re-selection
Selection Tolerance Windows	Resistors: $\pm 10\%$ ; Inductors & Capacitors: $\pm 25\%$
Baseline Derating Rules	Voltage: $\geq 1.2\times V_{\text{peak}}$ ; Current (MOSFET/Ind./Diode): $\geq 1.25\times I_{\text{rms/avg}}$
Circuit Simulator	ngspice 47 ( $T=27^{\circ}\text{C}$ , $\text{reltol}=10^{-4}$ , $\text{abstol}=1\,\mu\text{A}$ , $\text{vntol}=1\,\mu\text{V}$ )

Table 2: Summary of Core Implementation and Experimental Settings

Functional Role (Designator)	Theoretical / Ref.	Selected Nominal	Verified Part Number (Mfr.)	Qty
Case Study I: Non-Isolated Buck Converter (29 physical positions, 22 unique MPNs in total)
High-Side Switch ( QSW / Q1 )	$V_{\text{in,max}}=36\,\text{V}$	$600\,\text{V},41\,\text{m}\Omega$	IPW60R041P6FKSA1 (Infineon)	1
Freewheeling Diode ( DFREE / D1 )	$I_{\text{out}}=2\,\text{A}$	$200\,\text{V},3\,\text{A}$	UF3004-HF (Comchip)	1
Main Inductor ( LMAIN / L1 )	$166.67\,\mu\text{H}$	$180\,\mu\text{H}$	760800301 (Würth Elektronik)	1
Output Capacitor ( COUT / C1 )	$151.98\,\mu\text{F}$	$150\,\mu\text{F}$ ( $200\,\text{V}$ )	EKXJ201ELL151MJ50S (Chemi-Con)	1
Input Capacitor ( CIN / C2 )	$30.40\,\mu\text{F}$	$30\,\mu\text{F}$ ( $600\,\text{V}$ )	C44AHFP5300ZC0J (KEMET)	1

Table 3: Synthesized Parameters and Selected Core Commercial Components for Case Study I (Buck) and Case Study II (DAB)

Case (Eval. Window)	Test Condition	Operating Point	Max Step	Mean $V_{\text{out}}$ (V)	Mean $I_{\text{out}}$ (A)	Ripple $V_{\text{pp}}$ (V) / Status
Buck	vin_low	$24\,\text{V}/6\,\Omega$	$312.5\,\text{ns}$	$11.8639$	$1.9773$	$0.0671$ ( PASS )
(6.4–8.0 ms)	vin_high	$36\,\text{V}/6\,\Omega$	$312.5\,\text{ns}$	$11.8363$	$1.9727$	$0.0693$ ( PASS )
	half_load	$24\,\text{V}/12\,\Omega$	$312.5\,\text{ns}$	$11.8926$	$0.9910$	$0.1399$ ( PASS )
	fine_timestep	$24\,\text{V}/6\,\Omega$	$156.25\,\text{ns}$	$11.8639$	$1.9773$	$0.0670$ ( PASS )
DAB	nominal	$48\,\text{V}/48\,\Omega$ ( $\phi=0.06$ )	$166.7\,\text{ns}$	$22.7423$	$0.4738$	$0.1788$ ( PASS )
(4.8–6.0 ms)	fine_timestep	$48\,\text{V}/48\,\Omega$ ( $\phi=0.06$ )	$83.3\,\text{ns}$	$22.7422$	$0.4738$	$0.1795$ ( PASS )

Table 4: NGSPICE Reference Verification Results Across Operating Conditions for Case Study I (Buck) and Case Study II (DAB)

Panel of Figure 3 — Figure 3: Simulated ngspice startup and steady-state output voltage ( $V_{\text{out}}$ ) waveforms under full-load and half-load operating conditions without closed-loop feedback controllers: (a) Buck converter operating under a fixed PWM duty cycle at full load ( $R=6\,\Omega$ ) and half load ( $R=12\,\Omega$ ) against the $12\,\text{V}$ target; and (b) DAB converter operating under topology-synthesized single-phase-shift (SPS) angles at full load ( $R=48\,\Omega$ , phase $=21.600^{\circ}$ ) and half load ( $R=96\,\Omega$ , phase $=12.843^{\circ}$ ) against the $24\,\text{V}$ target.

Evaluation Metric	Proposed Framework	Vanilla LLM (One-Shot)
Verified Part Positions (All Enumerated Positions)	98.6% (70 / 71)	22.2% (4 / 18)
Verified Power-Core Component Positions †	94.4% (17 / 18)	15.4% (2 / 13)
Verified Unique Part Numbers (Deduplicated MPNs)	100.0% (17 / 17)	21.4% (3 / 14)
Source Nominal Value Consistency with Design Target	97.7% (43 / 44)	0.0% (0 / 7)
Reference Parameter Evidence Coverage (Audited Fields)	97.0% (162 / 167)	7.5% (4 / 53)
Switch Control Reference Consistency (Gate-Return to Source)	100.0% (9 / 9)	60.0% (3 / 5)

Table 5: Quantitative Comparison Between the Proposed Complete Workflow and the Vanilla LLM Baseline Across the Frozen Buck and DAB Benchmark Tasks

Audit Dimension	Case & Pos.	Vanilla LLM Output & Failure Mode	Proposed Framework Output & Verification
Nominal Value Match	Buck R_ESR vs. RCS	RC0402FR-0710RL : Target $10\,\text{m}\Omega$ , actual datasheet value is $10\,\Omega$ ( $1000\times$ error , FAIL ).	SL1TTE3L9J : Target $3.85\,\text{m}\Omega$ , actual part is $3.9\,\text{m}\Omega$ ( Within $\pm 10\%$ window , PASS ).
Capacitor Voltage Derating	Buck CIN ( $36\,\text{V}$ ) Buck COUT ( $12\,\text{V}$ )	T491A476K010AT : Rated $10\,\text{V}<36\,\text{V}$ bus . GRM32EC71A107KE15L : Rated $10\,\text{V}<12\,\text{V}$ out (Severe overvoltage conflict).	C44AHFP5300ZC0J : Rated $600\,\text{V}\gg 36\,\text{V}$ . EKXJ201ELL151MJ50S : Rated $200\,\text{V}\gg 12\,\text{V}$ (Sufficient safety margins).
Magnetic Realization	DAB T1 & L_SER	DAB_XFMR_2_1 & DAB_LEAKAGE_IND : Unverified custom text placeholders.	HPH6-0325L (4P:2S winding config.) & ATCA-01-101M-V : Verified COTS magnetics.
Controller Role & Ratings	Buck CONTROL	TPS54331DDCR : $28\,\text{V}_{\max}$ , $570\,\text{kHz}$ integrated-FET IC misused for $36\,\text{V}$ , $80\,\text{kHz}$ external FET.	UCC28C53DR + UCC27714D : Verified $80\,\text{kHz}$ current-mode PWM & gate driver.
Power-Stage Connectivity	Buck & DAB Netlists	Input/output nodes shunted only to caps; shorted gate sources ( Singular matrix, 0% sim pass ).	Complete power-stage & driver loop ( 100% convergence & spec pass ).

Table 6: Diagnostic Breakdown of Representative Component and Structural Failures in Vanilla LLM vs. Proposed Framework

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