Dynamic Powergrid Optimization with FPGA-based Neuromorphic Higher-order Ising Machines

Saptarshi Maiti; Shantanu Chakrabartty; Chetan Singh Thakur

cs.NEOct 29, 2026

Dynamic Powergrid Optimization with FPGA-based Neuromorphic Higher-order Ising Machines

Authors: Saptarshi Maiti, Shantanu Chakrabartty, Chetan Singh Thakur

Organizations: Department of Electronic Systems Engineering, Indian Institute of Science, Bangalore, India · Department of Electrical and Systems Engineering, Washington University in St. Louis, St. Louis, MO, USA

Abstract

The advent of large, high-density FPGAs such as the AMD Versal enables efficient hardware implementation of neuromorphic Ising machines, unlocking unprecedented performance for complex combinatorial optimizations. A critical application for this computing paradigm is dynamic powergrid optimization, specifically Distribution Network Reconfiguration (DNR), which seeks to mitigate severe resistive losses and reduce electricity costs by optimizing network switch configurations in real time. This paper presents an FPGA-based neuromorphic higher-order Ising machine for high-speed, adaptive DNR. By directly mapping DNR onto higher-order Ising interactions via a polynomial unconstrained binary optimization (PUBO) formulation, the proposed architecture requires only 179 spins for the IEEE 33-bus network, which represents a 6 times reduction compared to standard quadratic formulations. Implemented on an AMD Versal Premium VP1802 FPGA, the architecture executes parallel spin-group updates every 20 ns and solves 33-, 51-, and 69-bus benchmark networks with median latencies of 1.6-29.3 ms, yielding a 7-58 times speedup over Gurobi to the first optimal solution. Using the solver with expanded network-switching flexibility reduces power loss by 80.71 kW (57.83%), while adaptive reconfiguration every 10 s under time-varying demand saves 131.16 kWh/day over static daily reconfiguration, highlighting the potential of higher-order Ising hardware for fast, adaptive smart grid management.

Figures & tables

Fig. 1: Overview of FPGA-based neuromorphic Ising optimization for distribution network reconfiguration under dynamically changing load conditions.

Method	$\mathbf{e}$	$\mathbf{d}$	$\mathbf{p}$	$\mathbf{z}$	$\mathbf{y}$	Aux.	Total
QUBO [ 18 ]	24	4	23	577	434	12	1074
PUBO (ours)	24	4	23	128	0	0	179

TABLE I: Binary-variable comparison for the IEEE 33-bus network

Fig. 2: Architecture of the FPGA-based neuromorphic higher-order Ising machine, showing the two-layer architecture, interaction mapping, parallel spin-update datapaths, clause-state updates, and evaluation and tracking.

Network	Spins	Terms (pruned)	C / L	LUTs (%)	FFs (%)
IEEE-33	179	20,300 (20,300)	31/17	217.9k (6.48)	69.5k (1.03)
Cairo-51	141	49,187 (44,699)	48/10	594.3k (17.68)	174.6k (2.60)
IEEE-69	385	54,945 (25,237)	51/22	221.7k (6.60)	32.2k (0.48)

TABLE II: FPGA implementation on AMD Versal VP1802 at 50 MHz

Fig. 3: Ising optimization and benchmarking results. (a) Evolution of the Ising objective (scaled) and valid power loss for IEEE-33, with an inset showing convergence near the optimum. (b) Success probability versus median first-hit latency for different annealing budgets; error bars indicate Wilson 95% confidence intervals. (c) IEEE-33 runtime comparison with classical solvers [ 19 ] (d) Median latency of Ising and Gurobi across three distribution networks.

Fig. 4: Application-level DNR optimization using an Ising machine. (a) AC power-loss savings in the IEEE 33-bus network as additional candidate switches increase network flexibility. (b) AC energy savings versus reconfiguration interval under time-varying power demand throughout the day.

Method	Study	Implementation	Latency
Graph-based Genetic Algorithm	[ 27 ]	MATLAB	6 s
Chaotic Stochastic Fractal Search	[ 28 ]	MATLAB / CPU	49.59 s
Particle Swarm Optimization	[ 29 ]	MATLAB	120.25 s
QUBO / Hybrid Quantum Annealing	[ 19 ]	D-Wave hybrid	60 s
Mixed-Integer Quadratic Programming	[ 19 ]	Xpress / CPU	48 s
Mixed-Integer Quadratic Programming	[ 19 ]	CPLEX / CPU	316 s

TABLE III: Comparison of DNR Solvers on IEEE 33-Bus Network.

FPGA Acceleration

FPGA acceleration uses reconfigurable logic to speed compute-intensive workloads with hardware tailored to their needs.

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Apr 18, 2026J/K move · Enter open · S save

A fully parallel densely connected probabilistic Ising machine with inertia for real-time applications

Ruomin Zhu, Abhishek Kumar Singh, Jérémie Laydevant, Fan O. Wu+4

School of Applied and Engineering Physics, Cornell University, Ithaca, NY 14853, USA · Department of Computer Science, Princeton University, Princeton, NJ, 08540, USA · USRA Research Institute for Advanced Computer Science, Moffett Field, CA, 94035, USA+1

Ising Optimization

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Ising machines---special-purpose hardware for heuristically solving Ising optimization problems---based on probabilistic bits (p-bits) have been established as a promising alternative to heuristic optimization algorithms run on conventional computers. However, it has---until now---been thought that Ising spins that are connected in probabilistic Ising machines (PIMs) cannot be updated in parallel without ruining the machine's solving ability. This has presented a major challenge to realizing the potential for probabilistic Ising machines to act as fast solvers for densely connected Ising problems. In this paper, we show that it is possible to circumvent this conventional wisdom. We introduce a modified form of Ising spin dynamics for PIMs, adding an inertia term, and verify in algorithm simulations, field-programmable gate array (FPGA) emulation, and in FPGA experiments that the modified dynamics enables fully parallel, synchronous updates and at the same time improves the achieved success probability. Our evaluations were performed with various types of abstract (Max-Cut and Sherrington-Kirkpatrick model) and application-derived (multiple-input and multiple-output, MIMO detection) dense Ising benchmark instances. Performing fully parallel updates results in a speed advantage that grows superlinearly with the number of spins, giving rise to large time-to-solution reductions for practical problem sizes. For both MC and the SK model at a problem size of 200, our approach achieved an average speedup of ~34x, with the best single-instance speedup reaching 150x. As an example of the practical utility of our approach in an application where speed is critical, we co-design the algorithm dynamics and hardware implementation for MIMO detection, achieving improved detection accuracy relative to the standard linear detector and higher throughput than the conventional sequential-update PIM.

Abstract

FPGA Acceleration

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