A Surrogate Model for Variation-Aware Clock-Mesh Analysis and Design-Space Exploration using Graph Neural Networks

Muhammad Hadir Khan; Wajid Ali; Arya Thottiparambil Manikandan; Matthew Guthaus

cs.ARNov 1, 2026

A Surrogate Model for Variation-Aware Clock-Mesh Analysis and Design-Space Exploration using Graph Neural Networks

Authors: Muhammad Hadir Khan, Wajid Ali, Arya Thottiparambil Manikandan, Matthew Guthaus

Organizations: University of California, Santa Cruz, USA

Abstract

Clock meshes are widely used in high-performance VLSI systems to minimize skew and tolerate On-Chip Variation (OCV) in nanometer technologies. However, analyzing meshes is difficult because reconvergent paths and multi-source drivers prevent static timing analysis (STA) tools from handling mesh loops, making SPICE the industrial standard. SPICE simulations are accurate but slow, so clock-mesh synthesis relies on approximate models that overlook critical effects such as non-linear buffer driving caused by input slew and input skew. We propose a Graph Neural Network (GNN) based surrogate model of the clock mesh with a new graph representation and a new architecture that predicts power while also improving the delay and slew predictions at the sinks and capturing the skew histogram under OCV. Trained on SPICE data and tested on unseen real designs, our model achieves average errors of $3.40$ ~ps in delay, $4.14$ ~ps in slew and $4.46$ ~ps in skew, compared with $6.28$ ~ps, $12.35$ ~ps, and $11.62$ ~ps for our prior model, and $74.37$ ~ps delay and $27.51$ ~ps skew for the approximate method used in current state-of-the-art works. Our model predicts power within $3.4\%$ of SPICE on average, while delivering $18\times$ - $1706\times$ speed-ups over the approximate method under OCV modeling, enabling faster and more accurate clock-mesh design-space exploration. A case study on a real design further shows that our surrogate model finds buffering candidates that, at a balanced tradeoff, improves $99^{\text{th}}$ -percentile skew by $49.1\%$ , reduces power by $25.7\%$ , and reduces area by $37.3\%$ at the cost of a $6.8\%$ increase in $99^{\text{th}}$ -percentile maximum slew as compared to the state-of-the-art work.

Figures & tables

Figure 1. A clock tree driving the root clock to the mesh buffers through clock tree buffers. The redundant paths improve the tolerance to variations.

Figure 2. Breakdown of total power consumption in clock meshes. The short-circuit power contributes significantly to the total power which is obtained by running SPICE.

Figure 3. Left: A trivial clock-mesh grid example with buffering and sinks. Middle: Equivalent RC mesh network. Right: Our graph model representation.

Type	Name (units)	Description
Node features	input_delay (ps)	Buffer input delay from tree
	input_slew (ps)	Buffer input slew from tree
	buf_cap (fF)	Buffer effective capacitance
	buf_res (ohms)	Buffer effective resistance
	buf_len (nm)	Buffer channel length
	buf_vdd (V)	Buffer VDD supply

Table 1. Node/Edge features and labels.

Figure 4. Calculation of the RC edge features between sink (S0) and its two nearby mesh nodes (M0, M1) and between two adjacent mesh nodes. (S1) follows similar pattern.

Figure 5. Our model architecture uses

\boldsymbol{K}=4

GAT layers to perform message passing followed by normalization and ELU activation. Final node embeddings

\boldsymbol{X^{K}}

are used by separate MLP heads for delay and slew prediction and pooled to perform global tasks such as delay quantile predictions and power prediction.

Parameter	Layers	Channels	Attn. Heads
GAT	4	128	8
Delay/Slew/Quantile/Power MLP	3	64	N/A
Global Proj. MLP	2	64	N/A

Table 2. Model Parameters

Statistic	Ranges	Description
sink count	$[500,15000]$	Sets the size of the clock mesh.
sink density (sinks/ $\mu m^{2}$ )	$[0.037,0.86]$	Sinks per unit area; jointly with sink count it sets the die dimensions.
spatial uniformity ratio	$[0.4,1.2]$	Sink placement pattern, clustered ( $<1$ ) random ( $\approx 1$ ), or regular ( $>1$ ).
blockage ratio	$[0.0,0.65]$	Fraction of the die area obstructed by blockages.

Table 3. Statistics for synthetic benchmark generation

Figure 6. Synthetic Clock Meshes. Row 1: Shows different designs with varying statistics from Table 3 . Row 2: Shows a single design with varying buffer densities. The green rectangles are the blockages and red triangles are buffers.

Parameter (Affects)	Gaussian $(\boldsymbol{\sigma}/\boldsymbol{\mu})$	From
$L_{eff}$ (buf_len)	$0.84/21$ (nm)	( Masoumian et al., 2022 )
$W_{eff}$ (buf_cap/res,sink_cap)	$0.26/6.5$ (nm)	( Masoumian et al., 2022 )
$V_{th}$ (buf_vth)	$0.021/0.3$ (V)	( Wang et al., 2011 )
$V_{dd}$ (buf_vdd)	$0.023/0.7$ (V)	( Clark et al., 2016 )
Wire resistance (wire_res)	$0.003/0.02$ ( $\Omega/$ nm)	( Prasad et al., 2016 )
Wire capacitance (wire_cap)	$5.4e^{-6}/1.8e^{-4}$ (fF $/$ nm)	( Prasad et al., 2016 )

Table 4. Variation Parameters for OCV. The (Affects) shows which variation parameter changes which graph node/edge feature.

design	(ps)	(ps)	# Samples $\geq 3\sigma$	$f$	expected	$99\%$ conf.
	skew mean	$\text{ skew (mean}+3\sigma)$	# Samples $\geq 3\sigma$	$f$	SPICE samples $N$
ibex	29.8	49.1	41	0.82%	122	559
floonoc	33.3	46.7	34	0.68%	147	676
jpeg	33.5	49.8	31	0.62%	161	740
riscv32i	31.0	54.9	28	0.56%	179	820
mock-alu	20.4	35.6	28	0.56%	179	820

Table 5. Rarity of tail-producing skews under uniform Monte Carlo sampling. For each design,

5000

variations were drawn and SPICE-simulated. Where

f

denotes the measured fraction of corners whose skew reaches the mean

+3\sigma

threshold. Since draws are independent,

P(\text{at least one in }N)=1-(1-f)^{N}

, giving

N=1/f

on average and

N=\ln(0.01)/\ln(1-f)\approx 4.6/f

for

99\%

confidence.

Figure 7. Proposed Tail-Aware Loss function. Each sink node is assigned a normalized rank

r_{i}\in[0,1]

based on its ground-truth delay. The function assigns higher weight to the fastest and slowest sinks (shaded tail regions) compared to median sinks. Orange dots represent example sink nodes in a mesh, where the majority cluster near the median with few sinks at the tails.

Figure 8. Finetuning of the base model in the Active Learning loop. The GNN message passing layers are frozen and two additional Pre-Message and Post-Message MLPs are added to finetune to the data. The final embeddings are passed to the downstream MLPs in a similar manner as in Fig. 5 .

Synthetic Benchmarks	Stats
Synthetic Benchmarks	Area ( $\mu m^{2}$ )	Sinks	Grid Size	Blockages
synth_00	6294.0	5024	19x19	15
synth_01	6197.0	1082	10x10	6
synth_02	2846.9	1661	12x12	5
synth_03	3795.6	1858	12x12	0
synth_04	31063.4	13660	33x33	3

Table 6. Statistics of the test dataset that we evaluate our model on

Figure 9. Comparison of different model inference capabilities on a buffering density search space. For each buffering density, we do

20

random bufferings of ibex and run SPICE to compare the model’s inference with actual labels. Both the FASM models converge inside shaded prior work ( Khan and Guthaus, 2026 ) training range however, FASM-old is much more inaccurate for out-of-distribution bufferings as compared to FASM-new. Whereas, our proposed model in this work produces the least error in all the buffering density ranges.

Figure 10. Ablation study showing individual improvements of the proposed graph representation and model architecture on the real designs. Each bar represents the mean error over

100

Monte-Carlo corners per design.

Design	FASM	This Work	Red.	FASM	This Work	Red.	FASM	This Work	Red.
	Graph Nodes			Graph Edges			Peak GPU mem. (MB)
riscv32i	5,724	1,128	$5.07\times$	18,384	4,720	$3.89\times$	280	55	$5.09\times$
mock-alu	8,001	1,557	$5.14\times$	25,776	6,708	$3.84\times$	395	77	$5.13\times$
ibex	10,596	2,076	$5.10\times$	34,080	8,784	$3.88\times$	521	102	$5.11\times$
jpeg	24,595	4,783	$5.14\times$	79,248	20,572	$3.85\times$	1,206	237	$5.09\times$
cva6	26,237	5,157	$5.09\times$	84,320	21,624	$3.90\times$	1,284	251	$5.11\times$

Table 7. Graph representation scalability comparison with FASM. In the last row the node and edge entries are totals and their reduction is the combined ratio. Peak GPU memory is calculated over a single inference pass, measured with matched models so the difference is only due to the graph representation.

Designs	Delay MAE (ps)				Slew MAE (ps)		Skew error (ps)
Designs	This Work	FASM-new	FM	FM+cal	This Work	FASM-new	This Work	FASM-new	FM	FM+cal
synth_00	5.11	6.48	74.07	9.52	5.40	10.17	0.91	20.51	21.32	21.32
synth_01	6.59	14.76	63.96	9.46	10.93	25.12	7.41	8.58	35.86	35.86
synth_02	2.62	4.13	75.13	4.01	4.46	12.74	7.39	9.13	16.11	16.11
synth_03	3.91	4.39	81.71	5.62	4.23	9.75	11.11	14.56	35.28	35.28
synth_04	3.26	5.12	75.79	5.98	4.20	8.18	2.32	9.46	41.25	41.25

Table 8. Clock mesh timing metric prediction with this work, FASM-new ( Khan and Guthaus, 2026 ) , first-moment (FM) ( Kang and Kim, 2014 ; Rajaram and Pan, 2010 ; Li et al., 2025 ) , and its idealized calibrated variant FM+cal (Section 5.1 ) on the synthetic test set with one MC sample and HSPICE labels as golden reference. Skew is a sink-pair difference and is identical under FM and FM+cal. Also, FM provides no slew estimate so omitted from table.

Synthetic designs	Power (mW)			Error (%)
Synthetic designs	This Work	SPICE	Dynamic Power	This Work	Dynamic Power
synth_00	8.73	8.35	5.18	4.5%	37.9%
synth_01	2.31	2.27	1.47	1.9%	35.3%
synth_02	4.43	4.53	2.65	2.2%	41.5%
synth_03	4.66	4.82	2.66	3.3%	44.6%
synth_04	37.67	36.98	20.02	1.8%	45.9%

Table 9. Clock mesh power comparison of this work, Dynamic Power (

CV^{2}f

) and actual power from running HSPICE on the synthetic benchmarks.

Designs	Metric (ps)	This Work			FASM-new	FM	FM+cal
Designs	Metric (ps)	w/o AL	AL w/o Tail-Loss	AL w/ Tail-Loss	FASM-new	FM	FM+cal
riscv32i	Delay MAE	3.58	3.40	3.69	6.40	74.44	5.30
	Slew MAE	4.53	4.46	4.27	10.98	–	–
	Skew Error (avg.)	2.07	0.32	1.81	5.57	25.53	25.53
	Skew P99.9 Error	10.94	3.51	0.82	3.95	54.78	54.78
mock-alu	Delay MAE	3.41	3.36	3.59	5.18	75.63	3.63

Table 10. OCV model accuracy on the real designs, evaluated on 5000 SPICE-simulated MC corners per design. We report per-sink Mean Absolute Error (MAE) for delay and slew, and two distribution-level skew metrics: the average skew error,

|\text{mean(skew}_{\text{pred}})-~\!\text{mean(skew}_{\text{SPICE}})|

, and the tail skew error,

|\text{P99.9}_{\text{pred}}-\text{P99.9}_{\text{SPICE}}|

, computed over each design’s skew distribution. Our model is shown in three variants: trained without active learning (w/o AL), with AL under the default MSE loss (AL w/o Tail-Loss), and with AL under the proposed Tail-Loss (AL w/ Tail-Loss). FM+cal is the idealized per-corner calibrated FM of Section 5.1 . Skew is a sink-pair difference and is therefore identical under FM and FM+cal, and FM provides no slew estimate (–).

Panel of Figure 11 — Figure 11. Skew histogram plots of the two benchmarks (ibex, riscv32i). Left: plots shows the overall skew histogram produced by SPICE, and our three model variants. Right: plots shows the zoomed in tail-end of the skew histogram and how each model captures it.

Real Designs	Power (mW)			Error (%)
Real Designs	This Work	SPICE	Dynamic Power	This Work	Dynamic Power
riscv32i	2.38	2.45	1.44	3.8%	41.2%
mock-alu	3.47	3.36	1.88	3.7%	44.1%
ibex	4.69	4.66	2.69	2.0%	42.3%
jpeg	10.36	10.00	5.89	3.8%	41.1%
cva6	9.54	9.21	5.75	3.7%	37.6%

Table 11. Clock mesh power comparison of this work, the dynamic power estimate (

CV^{2}f

), and actual HSPICE power on real designs, averaged over 5000 MC corners per design. Error is the mean per-corner absolute percentage error against SPICE.

Design	Runtime (s)						Speedup of This Work
	HSPICE	FM	This Work		FASM		over FM		over FASM
	HSPICE	FM	graph conv.	infer.	graph conv.	infer.	1 pass	5000 MC	1 pass	5000 MC
riscv32i	1.86	0.15	0.1781	0.0082	0.1999	0.0095	0.8 $\times$	18 $\times$	1.12 $\times$	1.16 $\times$
mock-alu	4.92	0.37	0.2564	0.0038	0.2903	0.0088	1.4 $\times$	96 $\times$	1.15 $\times$	2.30 $\times$
ibex	8.67	0.51	0.3550	0.0052	0.4032	0.0116	1.4 $\times$	97 $\times$	1.15 $\times$	2.22 $\times$
jpeg	28.03	3.56	0.8872	0.0069	1.3250	0.0269	4.0 $\times$	503 $\times$	1.51 $\times$	3.84 $\times$

Table 12. Runtime for one mesh evaluation and for a 5000-sample Monte-Carlo sweep. We denote the SPICE netlist to graph conversion time as ( graph conv. ) and model inference time as ( infer. ). Under variation our model reuse a single converted graph and update only its features, so conversion is paid once. FM must be recomputed per corner.

	skew (ps)			max. slew (ps)			power	area	#
ibex design	$p_{50}$	$p_{99}$	$p_{99.9}$	$p_{50}$	$p_{99}$	$p_{99.9}$	(mW)	( $\mu$ m 2 )	bufs
baseline ( Venkataraman et al., 2006 )	29.1	48.2	53.5	94.5	105.3	108.6	4.71	54.37	128
MeshWorks ( Rajaram and Pan, 2010 )	21.1	37.3	43.0	98.4	112.4	117.6	2.75	27.77	139
Ours (min. slew)	11.6	22.2	26.7	106.5	117.3	120.2	2.13	18.63	139
Ours (balanced)	10.2	19.0	22.8	108.7	120.0	124.0	2.04	17.41	138
Ours (min. power)	10.9	20.7	24.4	111.2	122.6	127.2	1.97	16.45	129

Table 13. Buffering optimization on ibex , verified with 5000 HSPICE Monte Carlo corners per design at matched process seeds. Skew and maximum slew are reported as percentiles of the per-corner distribution, power is the mean.

vs. MeshWorks ( Rajaram and Pan, 2010 )
	skew		max. slew
ibex design	$p_{50}$	$p_{99}$	$p_{50}$	$p_{99}$	power	area
Ours (min. slew)	$+45.0\%$	$+40.5\%$	$-8.2\%$	$-4.4\%$	$+22.3\%$	$+32.9\%$
Ours (balanced)	$+51.7\%$	$+49.1\%$	$-10.5\%$	$-6.8\%$	$+25.7\%$	$+37.3\%$
Ours (min. power)	$+48.3\%$	$+44.5\%$	$-13.0\%$	$-9.1\%$	$+28.4\%$	$+40.8\%$
vs. baseline ( Venkataraman et al., 2006 )

Table 14. Relative change of the optimized buffering solutions with respect to each baseline, on the metrics of Table 13 . Skew and maximum slew are reported at the median (

p_{50}

) and the 99th percentile (

p_{99}

) over 5000 matched Monte Carlo corners, power is the mean and area is total buffer cell area. Positive values denote improvement.

Electronic Design Automation

Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.

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The University of Southern Mississippi, Hattiesburg, Mississippi, USA · Intel Corporation, Hillsboro, Oregon, USA · Louisiana Tech University, Ruston, Louisiana, USA

Graph Coarsening Electronic Design Automation Graph Neural Networks

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Graph Neural Networks (GNNs) are increasingly explored for physical design analysis in Electronic Design Automation, particularly for modeling Clock Tree Synthesis behavior such as clock skew and buffering complexity. However, practical deployment remains limited due to the prohibitive memory and runtime cost of operating on raw gate-level netlists. Graph coarsening is commonly used to improve scalability, yet its impact on CTS-critical learning objectives is not well characterized. This paper introduces CTS-Bench, a benchmark suite for systematically evaluating the trade-offs between graph coarsening, prediction accuracy, and computational efficiency in GNN-based CTS analysis. CTS-Bench consists of 4,860 converged physical design solutions spanning five architectures and provides paired raw gate-level and clustered graph representations derived from post-placement designs. Using clock skew prediction as a representative CTS task, we demonstrate a clear accuracy-efficiency trade-off. While graph coarsening reduces GPU memory usage by up to 17.2x and accelerates training by up to 3x, it also removes structural information essential for modeling clock distribution, frequently resulting in negative

R^2

scores under zero-shot evaluation. Our findings indicate that generic graph clustering techniques can fundamentally compromise CTS learning objectives, even when global physical metrics remain unchanged. CTS-Bench enables principled evaluation of CTS-aware graph coarsening strategies, supports benchmarking of GNN architectures and accelerators under realistic physical design constraints, and provides a foundation for developing learning-assisted CTS analysis and optimization techniques.

Abstract

Electronic Design Automation

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