FPGA Acceleration

Deep learning (DL) has emerged as a rapidly developing advanced technology, enabling the performance of complex tasks involving image recognition, natural language processing, and autonomous decision-making with high levels of accuracy. However, as these technologies evolve and strive to meet the growing demands of real-life applications, the complexity of DL models continues to increase. These models require processing of massive volumes of data, demanding substantial computational power and memory bandwidth. This gives rise to the critical need for hardware accelerators that can deliver both high performance and energy efficiency. Accelerator types include ASIC based solutions, GPU accelerators, and FPGA based implementations. The limitations of ASIC and GPU accelerators have led to FPGAs becoming one of the prominent solutions, offering distinct advantages for DL workloads. FPGAs provide a flexible and reconfigurable platform, allowing model specific customization while maintaining high efficiency. This article explores various hardware level optimizations for DL. These optimizations include techniques such as loop pipelining, parallelism, quantization, and various memory hierarchy enhancements. In addition, it provides an overview of state-of-the-art FPGA-based neural network accelerators. Through the study and analysis of these accelerators, several challenges have been identified, paving the way for future optimizations and innovations in the design of FPGA-based hardware accelerators.

Neuromorphic accelerators promise unparalleled energy efficiency and computational density for spiking neural networks, especially in wearable biomedical devices and neural prosthetics where power constraints are stringent. However, most existing platforms exhibit rigid architectures with limited configurability, restricting their adaptability to heterogeneous biological signals and diverse design objectives. To address these limitations, we present Flexi-NeurA--a flexible neuromorphic accelerator that unifies configurability and efficiency. Flexi-NeurA allows users to customize neuron models, network structures, and precision settings at design time. By pairing these design-time configurability features with a time-multiplexed and event-driven processing approach, Flexi-NeurA reduces the required hardware resources and total power while preserving high efficiency and low inference latency. Complementing this, we introduce Flex-plorer, a design-space exploration tool that determines cost-effective fixed-point precisions for critical parameters--such as decay factors, synaptic weights, and membrane potentials--based on user-defined trade-offs between accuracy and resource usage. Based on the configuration selected through the Flex-plorer process, RTL code is configured to match the specified design. Comprehensive evaluations across distinct domains--biomedical auditory processing, dynamic vision sensor gesture recognition, and standard vision classification--demonstrate that the hardware/software co-framework successfully balances accuracy and power budgets for diverse applications. A 3-layer 256-128-10 fully connected network with LIF neurons mapped onto two processing cores achieves 96.23% accuracy on MNIST with 1.1 ms inference latency, utilizing only 1,623 logic cells, 7 BRAMs, and 111 mW of total power--demonstrating superior resource efficiency compared to SoTA hardware baselines.

Space missions are becoming increasingly ambitious, necessitating high-performance onboard spacecraft computing systems. In response, field-programmable gate arrays (FPGAs) have garnered significant interest due to their flexibility, cost-effectiveness, and radiation tolerance potential. Concurrently, neural networks (NNs) are being recognized for their capability to execute space mission tasks such as autonomous operations, sensor data analysis, and data compression. This survey serves as a valuable resource for researchers aiming to implement FPGA-based NN accelerators in space applications. By analyzing existing literature, identifying trends and gaps, and proposing future research directions, this work highlights the potential of these accelerators to enhance onboard computing systems.