FPGA Acceleration

FPGA: Field-Programmable Gate Array

FPGA acceleration studies how to map computation onto field-programmable gate arrays, reconfigurable chips used for tasks such as neural-network inference, image and event processing, signal analysis, and real-time control. Common techniques include pipelining and parallel dataflow, fixed-point quantization, memory-local designs, and dividing workloads between FPGAs and CPUs or GPUs. Design tools, high-level synthesis, and emerging AI-assisted methods aim to automate the search for effective hardware architectures. A central challenge is balancing speed and energy use against limited logic and memory, while preserving accuracy and accounting for data movement and implementation reliability.

Latest papers

33 papers3 papers in the last four weeks, against 2 the four weeks before. 0.0% of all new papers.

Architectural Design and Performance Analysis of FPGA based AI Accelerators: A Comprehensive Review
Feb 25, 2026Soumita Chatterjee, Sudip Ghosh, Tamal Ghosh +1FPGA Acceleration FPGA-Based Neural Network Acceleration
Indian Institute of Engineering Science and Technology, Shibpur, India
Flexi-NeurA: A Flexible Neuromorphic Accelerator with Adaptive Bit-Precision Exploration for Edge Devices
Feb 20, 2026Mohammad Farahani, Mohammad Rasoul Roshanshah, Saeed SafariNeuromorphic Computing FPGA Acceleration
High-Performance Embedded Architecture Laboratory (HiPEAL), School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran
FPGA-Based Neural Network Accelerators for Space Applications: A Survey
Apr 22, 2025Pedro Antunes, Artur PodobasFPGA-Based Neural Network Acceleration FPGA Acceleration

Feb 25, 2026J/K move · Enter open · S save

Architectural Design and Performance Analysis of FPGA based AI Accelerators: A Comprehensive Review

Soumita Chatterjee, Sudip Ghosh, Tamal Ghosh, Hafizur Rahaman

Indian Institute of Engineering Science and Technology, Shibpur, India

FPGA Acceleration FPGA-Based Neural Network Acceleration Efficient Neural Network Inference Energy-Efficient ML

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Deep learning (DL) has emerged as a rapidly developing advanced technology, enabling the performance of complex tasks involving image recognition, natural language processing, and autonomous decision-making with high levels of accuracy. However, as these technologies evolve and strive to meet the growing demands of real-life applications, the complexity of DL models continues to increase. These models require processing of massive volumes of data, demanding substantial computational power and memory bandwidth. This gives rise to the critical need for hardware accelerators that can deliver both high performance and energy efficiency. Accelerator types include ASIC based solutions, GPU accelerators, and FPGA based implementations. The limitations of ASIC and GPU accelerators have led to FPGAs becoming one of the prominent solutions, offering distinct advantages for DL workloads. FPGAs provide a flexible and reconfigurable platform, allowing model specific customization while maintaining high efficiency. This article explores various hardware level optimizations for DL. These optimizations include techniques such as loop pipelining, parallelism, quantization, and various memory hierarchy enhancements. In addition, it provides an overview of state-of-the-art FPGA-based neural network accelerators. Through the study and analysis of these accelerators, several challenges have been identified, paving the way for future optimizations and innovations in the design of FPGA-based hardware accelerators.

Latest papers

Architectural Design and Performance Analysis of FPGA based AI Accelerators: A Comprehensive Review

Flexi-NeurA: A Flexible Neuromorphic Accelerator with Adaptive Bit-Precision Exploration for Edge Devices

FPGA-Based Neural Network Accelerators for Space Applications: A Survey