Hardware-Software Co-Design

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Hardware-software co-design studies how to shape algorithms, software, and hardware together so a complete system meets goals such as low latency, energy efficiency, or limited memory. Common approaches include quantization and pruning, workload-aware mapping and scheduling, specialized dataflows and accelerators, and joint design of sensors, robots, or other physical systems. Designers explore trade-offs with analytical models, simulators, synthesis tools, and increasingly hardware feedback or AI agents, then evaluate on workloads and deployment platforms. A central challenge is finding designs that remain effective across real workloads and hardware while keeping models, benchmarks, and physical validation reliable.

Latest papers

69 papers9 papers in the last four weeks, against 1 the four weeks before. 0.1% of all new papers.

MONET: Modeling and Optimization of neural NEtwork Training from Edge to Data Centers
Mar 16, 2026Jérémy Morlier, Robin Geens, Stef Cuyckens +4Hardware-Software Co-Design Memory-Efficient Training
IMT Atlantique, Brest, France. · MICAS, KU Leuven, Leuven, Belgium.
AI+HW 2035: Shaping the Next Decade
Mar 5, 2026Deming Chen, Jason Cong, Azalia Mirhoseini +27Hardware-Software Co-Design Energy-Efficient ML
University of Illinois Urbana-Champaign · University of California, Los Angeles · Stanford University +24
Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators
Mar 4, 2026Olga Krestinskaya, Mohammed E. Fouda, Ahmed Eltawil +1Compute-in-Memory Hardware-Software Co-Design
King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia · Compumacy for Artificial Intelligence Solutions, Cairo, Egypt
Amanous: Distribution-Switching for Superhuman Piano Density on Disklavier
Feb 28, 2026Joonhyung BaeSymbolic Music Generation Hardware-Software Co-Design
Graduate School of Culture Technology KAIST (Korea Advanced Institute of Science and Technology) Daejeon, South Korea
LLMServingSim 2.0: A Unified Simulator for Heterogeneous and Disaggregated LLM Serving Infrastructure
Feb 26, 2026Jaehong Cho, Hyunmin Choi, Guseul Heo +1LLM Serving Disaggregated LLM Serving
School of Computing KAIST Daejeon, South Korea
GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon
Feb 16, 2026Arya Tschand, Chenyu Wang, Zishen Wan +21Electronic Design Automation Hardware-Software Co-Design
Harvard University
Soft yet Effective Robots via Holistic Co-Design
Apr 20, 2025Maximilian Stölzle, Niccolò Pagliarani, Francesco Stella +6Hardware-Software Co-Design Soft Robotics
Laboratory for Information & Decision Systems, Massachusetts Institute of Technology, Cambridge, 02139, MA, USA. · Cognitive Robotics, Delft University of Technology, Mekelweg 2, Delft, 2628 CD, Netherlands. · Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, Cambridge, 02139, MA, USA. +4
Accelerating Stateful Network Applications with Performance Prediction on SoC SmartNICs
Oct 29, 2024Shaoke Xi, Jiaqi Gao, Fuliang Li +2Hardware-Software Co-Design
Alibaba Cloud · Northeastern University, China · Harvard University
Context-Aware System Synthesis, Task Assignment, and Routing
Jun 14, 2017Jason Ziglar, Ryan Williams, Alfred WicksCombinatorial Optimization Robotics

Mar 16, 2026J/K move · Enter open · S save

MONET: Modeling and Optimization of neural NEtwork Training from Edge to Data Centers

Jérémy Morlier, Robin Geens, Stef Cuyckens, Arne Symons+3

IMT Atlantique, Brest, France. · MICAS, KU Leuven, Leuven, Belgium.

Hardware-Software Co-Design Memory-Efficient Training

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While hardware-software co-design has significantly improved the efficiency of neural network inference, modeling the training phase remains a critical yet underexplored challenge. Training workloads impose distinct constraints, particularly regarding memory footprint and backpropagation complexity, which existing inference-focused tools fail to capture. This paper introduces MONET, a framework designed to model the training of neural networks on heterogeneous dataflow accelerators. MONET builds upon Stream, an experimentally verified framework that that models the inference of neural networks on heterogeneous dataflow accelerators with layer fusion. Using MONET, we explore the design space of ResNet-18 and a small GPT-2, demonstrating the framework's capability to model training workflows and find better hardware architectures. We then further examine problems that become more complex in neural network training due to the larger design space, such as determining the best layer-fusion configuration. Additionally, we use our framework to find interesting trade-offs in activation checkpointing, with the help of a genetic algorithm. Our findings highlight the importance of a holistic approach to hardware-software co-design for scalable and efficient deep learning deployment.