CTS-Bench: Benchmarking Graph Coarsening Trade-offs for GNNs in Clock Tree Synthesis

Barsat Khadka; Kawsher Roxy; Md Rubel Ahmed

cs.LGFeb 22, 2026

CTS-Bench: Benchmarking Graph Coarsening Trade-offs for GNNs in Clock Tree Synthesis

Authors: Barsat Khadka, Kawsher Roxy, Md Rubel Ahmed

Organizations: The University of Southern Mississippi, Hattiesburg, Mississippi, USA · Intel Corporation, Hillsboro, Oregon, USA · Louisiana Tech University, Ruston, Louisiana, USA

Abstract

Graph Neural Networks (GNNs) are increasingly explored for physical design analysis in Electronic Design Automation, particularly for modeling Clock Tree Synthesis behavior such as clock skew and buffering complexity. However, practical deployment remains limited due to the prohibitive memory and runtime cost of operating on raw gate-level netlists. Graph coarsening is commonly used to improve scalability, yet its impact on CTS-critical learning objectives is not well characterized. This paper introduces CTS-Bench, a benchmark suite for systematically evaluating the trade-offs between graph coarsening, prediction accuracy, and computational efficiency in GNN-based CTS analysis. CTS-Bench consists of 4,860 converged physical design solutions spanning five architectures and provides paired raw gate-level and clustered graph representations derived from post-placement designs. Using clock skew prediction as a representative CTS task, we demonstrate a clear accuracy-efficiency trade-off. While graph coarsening reduces GPU memory usage by up to 17.2x and accelerates training by up to 3x, it also removes structural information essential for modeling clock distribution, frequently resulting in negative $R^2$ scores under zero-shot evaluation. Our findings indicate that generic graph clustering techniques can fundamentally compromise CTS learning objectives, even when global physical metrics remain unchanged. CTS-Bench enables principled evaluation of CTS-aware graph coarsening strategies, supports benchmarking of GNN architectures and accelerators under realistic physical design constraints, and provides a foundation for developing learning-assisted CTS analysis and optimization techniques.

Figures & tables

Panel of Figure 1 — Figure 1. CTS-Bench benchmarks the trade-off between memory efficiency and model fidelity

Stage	Parameter	Range / Set	Type
Synthesis	Synth Strategy	{AREA 0-2, DELAY 0-4}	Categorical
Floorplan	Aspect Ratio	{0.7, 1.0, 1.4, 2.0}	Discrete
Floorplan	IO Mode	{Random Pin, Standard}	Binary (0/1)
Placement	Core Utilization	40% – 70%	Continuous
Placement	Target Density	$Util+[0.0,0.20]$	Continuous
Placement	Time Driven	{Enabled, Disabled}	Binary (0/1)

Table 1. Randomization Knobs for Data Diversity

Category	Metric	Unit
Timing	Skew (Setup/Hold), Slack, TNS	$ns$
Power	Total Dynamic/Static Power	$W$
Physical	Wirelength, Cell Utilization	$\mu m,\%$
Resources	Clock Buffers/Inverters Count	integer
Congestion	Routing/Repair Buffer Count	integer

Table 2. Labels used for QoR Metrics

Figure 3. Raw Nodes are nodes in ground truth graphs, and Clustered nodes are nodes after coarsening. Vertical variance shows sensitivity to placement-specific logic distribution.

Graph	Hid. Dim.	L. Rate	Plac. Dim.	CTS Dim.
Raw	64	0.001	32	16
Clustered	16	0.0005	8	4

Table 3. Model Hyper-parameters used in CTS-Bench

Figure 4. Efficiency benchmark comparing Raw and Clustered models in terms of Peak VRAM and execution time.

Figure 5. MAE Accuracy (bars, left y-axis) and Spatial

R^{2}

Fidelity (markers, right y-axis) across Skew, Power, and Wire metrics for the Raw Workload.

Figure 6. MAE Accuracy (bars, left axis) and Spatial

R^{2}

Fidelity (markers, right axis) across Skew, Power, and Wire metrics for the Clustered Workload.

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SwiftCTS: Fast Cross-Design Prediction and Pareto Optimization of Clock Tree Metrics via Few-Shot Calibration

Barsat Khadka, Kawsher Roxy, Md Rubel Ahmed

The University of Southern Mississippi Hattiesburg, MS, USA · Intel Corporation Hillsboro, OR, USA · Louisiana Tech University Ruston, LA, USA

Surrogate Modeling Surrogate-Assisted Optimization Model Calibration Physics-Informed ML

Open paper AskPDF arXiv

Clock Tree Synthesis (CTS) is a computationally expensive stage in the physical design flow, requiring iterative EDA tool invocations to navigate a vast configuration space for optimal power, wirelength, and timing skew. Existing machine learning approaches require computationally expensive retraining or fine-tuning cycles to adapt to unseen macro architectures and are architecturally mismatched to the millions of evaluations demanded by exhaustive combinatorial search. We present SwiftCTS, a physics-informed surrogate framework that addresses both limitations simultaneously. By coupling lightweight, physics-grounded statistical features with gradient-boosted ensembles, SwiftCTS trains in under five seconds on a CPU and delivers sub-millisecond inference without GPU support. To handle out-of-distribution (OOD) designs without retraining or fine-tuning, we introduce a K-shot multiplicative calibration mechanism that anchors predictions to just one or two physical reference runs, reducing power prediction error from 24.5% to 3.3% and wirelength error from 56.6% to under 1% on unseen macros. Integrating this engine with an evolutionary optimizer, SwiftCTS evaluates 100,000 CTS configurations in under ten seconds, yielding Pareto-optimal frontiers that are physically validated within the OpenROAD flow. Closed-loop validation confirms prediction errors below 0.5% for power and wirelength, and timing skew predictions within five picoseconds on an OOD benchmark, consistently outperforming default tool heuristics across all target metrics. Code publicly available at: https://github.com/BarsatKhadka/SwiftCTS

Abstract

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