Breaking the Tuning Barrier: Zero-Hyperparameters Yield Multi-Corner Analysis Via Learned Priors

Wei W. Xing; Kaiqi Huang; Jiazhan Liu; Hong Qiu; Shan Shen

cs.LGMar 13, 2026

Breaking the Tuning Barrier: Zero-Hyperparameters Yield Multi-Corner Analysis Via Learned Priors

Authors: Wei W. Xing, Kaiqi Huang, Jiazhan Liu, Hong Qiu, Shan Shen

Organizations: School of Mathematical and Physical Science, University of Sheffield, Sheffield, UK · SZU–UoS Joint Centre for Innovation and Entrepreneurship, College of Mechatronics and Control Engineering, Shenzhen University, China · Nanjing University of Science and Technology, China

Abstract

Yield Multi-Corner Analysis validates circuits across 25+ Process-Voltage-Temperature corners, resulting in a combinatorial simulation cost of $O(K \times N)$ where $K$ denotes corners and $N$ exceeds $10^4$ samples per corner. Existing methods face a fundamental trade-off: simple models achieve automation but fail on nonlinear circuits, while advanced AI models capture complex behaviors but require hours of hyperparameter tuning per design iteration, forming the Tuning Barrier. We break this barrier by replacing engineered priors (i.e., model specifications) with learned priors from a foundation model pre-trained on millions of regression tasks. This model performs in-context learning, instantly adapting to each circuit without tuning or retraining. Its attention mechanism automatically transfers knowledge across corners by identifying shared circuit physics between operating conditions. Combined with an automated feature selector (1152D to 48D), our method matches state-of-the-art accuracy (mean MREs as low as 0.11%) with zero tuning, reducing total validation cost by over $10\times$ .

Figures & tables

		OPT ( Liu et al., 2023 )	FUSIS ( Liu and Xing, 2025 )	ACS ( Shi et al., 2019 )	HSCS ( Wu et al., 2016 )
MRE (%)	Mean	45.25	79.36	69.18	74.94
	Std. Dev.	28.96	102.43	37.75	44.60
	Best (Min)	19.36	12.35	11.92	11.11
	Worst (Max)	111.24	346.32	100.00	137.78
#Sim.	Mean	461k	26k	147k	195k
	Std. Dev.	56k	5k	65k	99k

Table 1. Hyperparameter sensitivity of relative error and # sim. on 8

\times

2 SRAM with 10 configurations (

\pm 20\%

variation).

Figure 1. Automated YMCA framework. Sparse feature selection reduces the problem dimension within TabPFN’s capacity. The main loop alternates between in-context learning and uncertainty-driven active sampling until convergence.

Figure 2. Read current path of 6T SRAM cell from OpenYield benchmark suite ( Shen et al., 2025 ) .

Process Corner	TT	FF	SF	FS	SS
Voltage (V)	1.0	1.1	1.0	1.0	0.9
Temperature (C)	25	0	25	25	125
#Simulations	10k	10k	10k	10k	10k

Table 2. PVT Combinations used in our experiments. The process corners in the context represent a PVT combination.

Testcase	1	2	3	4
#Row	4	8	16	32
#Column	2	2	2	2
Delay Spec (ns)	0.0626	0.0745	0.113	0.209
#Process Para.	144	288	576	1152

Table 3. SRAM configurations used in our experiments. The number of rows spans 4–32, while the number of columns remains 2 for faster simulations.

Figure 3. Surrogate model comparison on 8 $\times$ 2 SRAM. TabPFN (red) exhibits superior data efficiency in the small-sample regime while requiring zero hyperparameter tuning.

Circuit	Method	TT			FF			SF			FS			SS
Circuit	Method	$Y$	$\hat{Y}$	MRE(%)	$Y$	$\hat{Y}$	MRE(%)	$Y$	$\hat{Y}$	MRE(%)	$Y$	$\hat{Y}$	MRE(%)	$Y$	$\hat{Y}$	MRE(%)
4 $\times$ 2	BI-BD	100	100	0	95.0	95.4	0.42	90.9	91.2	0.33	100	100	0	0	0	0
	BI-BC	100	100	0	95.0	96.4	1.47	90.9	91.6	0.77	100	100	0	0	0	0
	OPT	100	100	0	95.0	95.9	0.94	90.9	92.2	1.43	100	100	0	0	0	0
	Proposed	100	100	0	95.0	95.4	0.42	90.9	90.8	0.11	100	100	0	0	0	0
8 $\times$ 2	BI-BD	87.1	87.4	0.34	99.0	99.2	0.20	11.3	11.2	0.89	100	100	0	0	0	0

Table 4. Detailed yield predictions for all methods across PVT corners. Ground truth results

Y

(%) from 50,000-sample MC, predicted yield

\hat{Y}

(%), and MRE. The lowest MRE per corner is bolded.

Figure 4. Convergence on single challenging corner (8 $\times$ 2 SRAM, FF corner) of SOTA yield analysis methods.

Method	$\boldsymbol{P_{fail}}$	MRE (%)	#Sim.	Speedup
MC	$6.59\text{\times}{10}^{-3}$	—	$4100$	—
OPT	$6.00\text{\times}{10}^{-03}$	8.88	$3000$	$1.4\text{\times}$
MNIS	$5.75\text{\times}{10}^{-03}$	$12.63$	$3100$	$1.3\text{\times}$
ACS	$8.46\text{\times}{10}^{-3}$	$28.47$	$2700$	$1.5\text{\times}$
HSCS	$5.33\text{\times}{10}^{-3}$	$19.01$	$3360$	$1.2\text{\times}$
Proposed	6.00e-3	8.88	170	24.1x

Table 5. Single-corner performance on 8

\times

2 SRAM FF corner against 4,100-sample MC baseline.

	Additional Corners
Corner	Target Only	+1	+2	+3	+4	MRE Reduction
TT	21.79	13.85	10.86	9.05	6.04	$-72\%$
FF	0.00	0.00	0.00	0.00	0.00	—
SS	4.09	4.09	3.79	3.62	3.61	$-12\%$
SF	100.00	100.00	71.43	57.14	42.86	$-57\%$
FS	2.21	2.00	0.88	0.87	0.71	$-68\%$

Table 6. Ablation study demonstrating cross-corner knowledge transfer on 16

\times

2 SRAM. Each target corner uses 50 samples from itself, plus 50 samples from an unseen corner.

Surrogate Modeling

Surrogate modeling builds faster or more interpretable approximations of expensive simulations and black-box models.

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A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

Wenji Fang, Jing Wang, Yao Lu, Shang Liu+3

Hong Kong University of Science and Technology (HKUST), Hong Kong · Hong Kong University of Science and Technology (Guangzhou) (HKUST(GZ)), China

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Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications. Most recently, foundation AI models for circuits have emerged as a new technology trend. Unlike traditional task-specific AI solutions, these new AI models are developed through two stages: 1) self-supervised pre-training on a large amount of unlabeled data to learn intrinsic circuit properties; and 2) efficient fine-tuning for specific downstream applications, such as early-stage design quality evaluation, circuit-related context generation, and functional verification. This new paradigm brings many advantages: model generalization, less reliance on labeled circuit data, efficient adaptation to new tasks, and unprecedented generative capability. In this paper, we propose referring to AI models developed with this new paradigm as circuit foundation models (CFMs). This paper provides a comprehensive survey of the latest progress in circuit foundation models, unprecedentedly covering over 130 relevant works. Over 90% of our introduced works were published in or after 2022, indicating that this emerging research trend has attracted wide attention in a short period. In this survey, we propose to categorize all existing circuit foundation models into two primary types: 1) encoder-based methods performing general circuit representation learning for predictive tasks; and 2) decoder-based methods leveraging large language models (LLMs) for generative tasks. For our introduced works, we cover their input modalities, model architecture, pre-training strategies, domain adaptation techniques, and downstream design applications. In addition, this paper discussed the unique properties of circuits from the data perspective. These circuit properties have motivated many works in this domain and differentiated them from general AI techniques.

Abstract

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