SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization

Prashanth Vijayaraghavan; Apoorva Nitsure; Luyao Shi; Charles Mackin; Ashutosh Jadhav; David Beymer; Ehsan Degan; Vandana Mukherjee

cs.CLMar 17, 2026

SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization

Authors: Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi, Charles Mackin, Ashutosh Jadhav, David Beymer, Ehsan Degan, Vandana Mukherjee

Organizations: IBM Research, San Jose, CA, USA

Abstract

Register-Transfer Level (RTL) synthesis and summarization are central to hardware design automation but remain challenging for Large Language Models (LLMs) due to rigid HDL syntax, limited supervision, and weak alignment with natural language. Existing prompting and retrieval-augmented generation (RAG) methods have not incorporated symbolic planning, limiting their structural precision. We introduce SYMDIREC, a neuro-symbolic framework that decomposes RTL tasks into symbolic subgoals, retrieves relevant code via a fine-tuned retriever, and assembles verified outputs through LLM reasoning. Supporting both Verilog and VHDL without LLM fine-tuning, SYMDIREC achieves ~20% higher Pass@1 rates for synthesis and 15-20% ROUGE-L improvements for summarization over prompting and RAG baselines, demonstrating the benefits of symbolic guidance in RTL tasks.

Figures & tables

Figure 1: Overview of our SymDiReC framework for RTL synthesis and summarization.

Figure 2: Illustration of our SymDiReC framework for 8-bit carry ripple adder.

Method	LLM	Pass@1		Rouge - L
		Verilog	VHDL	Verilog	VHDL
Vanilla Prompting	GPT - 4o	$0.543$	$0.285$	$43.1$	$39.3$
Vanilla Prompting	Llama - 3	$0.385$	$0.226$	$40.2$	$34.1$
CoDes	GPT - 4o	$0.602$	$0.348$	$46.9$	$43.2$
CoDes	Llama - 3	$0.435$	$0.274$	$43.5$	$39.5$
ReAct Prompting	GPT - 4o	$0.616$	$0.353$	$46.1$	$43.0$

Table 1: RTL synthesis (Pass@1) and summarization ( Rouge-L ) performance across methods and LLMs. For our SymDiReC , mean

\pm

standard deviation over five independent runs is reported. Results are statistically significant vs. the strongest baseline (paired t - test,

p<0.01

). ∗ indicates results reported in the original papers.

Figure 3: Ablation results: Performance with varying (a) number of sub-components and (b) chunking strategy.

RTL-IR Dataset Statistics
# Total Size	$\sim 50.5$ k
# Text-to-Code Pairs	$\sim 8$ k
# FEC Pairs	$\sim 13.5$ k
# Code-to-Summary Pairs	$\sim 6.5$ k
# Partial-to-Complete Code Pairs	$\sim 22.5$ k

Table 2: Dataset statistics of RTL-IR used for model finetuning and retrieval enhancement.

Appendix figures & tables3 assets

Supplementary material from the paper’s appendix.

Appendix

Figure 4: VHDL Samples of different transformation strategies applied using the three categories of code clones – Type 2, Type 3 and Type 4.

Methods	NDCG@1	NDCG@10
BM25	0.434	0.570
ELSER	0.485	0.664
SPLADE	0.577	0.688
GTE-Qwen-1.5b	0.644	0.864
Stella-400m	0.656	0.866
GIST-Large	0.616	0.802

Appendix

Table 3: Evaluation of sparse, hybrid, and dense retrievers on RTL-IR test set.

Task	Symbolic Decomposition	Retrieved Context
8-bit Ripple Carry Adder	LSB Half-Adder: $S_{0}=A_{0}\oplus B_{0}$ , $C_{1}=A_{0}\land B_{0}$ Bits 1–7 Full-Adders: $S_{i}=A_{i}\oplus B_{i}\oplus C_{i}$ , $C_{i+1}=(A_{i}\land B_{i})\lor(B_{i}\land C_{i})\lor(A_{i}\land C_{i})$	Half-Adder (LSB) Verilog: module half_adder(input a, b, o utput sum, carry); assign sum = a ^ b; assign carry = a & b; endmodule VHDL: entity half_adder is port(a, b: in std_logic; sum, carry: out std_logic); end entity; architecture rtl of half_adder is begin sum <= a xor b; carry <= a and b; end architecture; Full-Adder (bits 1–7) Verilog: module full_adder(input a, b, cin, output sum, cout); assign sum = a ^ b ^ cin; assign cout = (a & b) \| (b & cin) \| (a & cin); endmodule VHDL: entity full_adder is port(a, b, cin: in std_logic; sum, cout: out std_logic); end entity; architecture rtl of full_adder is begin sum <= a xor b xor cin; cout <= (a and b) or (b and cin) or (a and cin); end architecture;

Appendix

Table 4: Qualitative example for 8-bit ripple carry adder. Symbolic decomposition shows Boolean/logical expressions for each submodule. Retrieved context contains modular Verilog and VHDL code snippets corresponding to these submodules. All submodules passed simulation/testbench.

Electronic Design Automation

Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.

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StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis

Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi, Ehsan Degan+1

IBM Research San Jose, CA, USA

RL for Code Generation Process Reward Models Electronic Design Automation Code Generation LLM-Based Program Synthesis RTL Code Generation

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Automatic generation of RTL code for digital hardware designs remains challenging due to long-horizon reasoning, multi-step dependencies, and strict correctness constraints in Verilog and VHDL. We present StepPRM-RTL, a novel framework that combines stepwise trajectory modeling, process-reward modeling (PRM), and retrieval-augmented fine-tuning (RAFT) to enhance both the functional correctness and reasoning fidelity of LLM-based RTL code generation. StepPRM-RTL constructs stepwise reasoning trajectories from canonical solutions, where each step contains a rationale and incremental code modification. A Process Reward Model (PRM) evaluates intermediate steps, providing dense feedback that guides reinforcement-style updates during RAFT fine-tuning. Monte Carlo Tree Search (MCTS) explores alternative reasoning paths, enriching the training dataset with high-quality trajectories. This integration of stepwise and outcome-aware rewards allows the model to learn both how and why to construct correct RTL, improving long-horizon reasoning beyond standard supervised or outcome-based training. Experimental evaluation on benchmark Verilog and VHDL datasets demonstrates that StepPRM-RTL outperforms the best prior methods by over 10% in functional correctness and reasoning fidelity metrics. Ablation studies confirm that the combination of PRM-guided rewards and stepwise trajectory exploration is key to its performance. StepPRM-RTL generalizes across RTL languages and provides a scalable framework for high-fidelity, interpretable code generation, establishing a new standard for LLM-assisted hardware design automation.

Abstract

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