GenAI Units In Digital Design Education (GUIDE) is an open courseware repository with runnable Google Colab labs and other materials. We describe the repository's architecture and educational approach based on standardized teaching units comprising slides, short videos, runnable labs, and related papers. This organization enables consistency for both the students' learning experience and the reuse and grading by instructors. We demonstrate GUIDE in practice with three representative units: VeriThoughts for reasoning and formal-verification-backed RTL generation, enhanced LLM-aided testbench generation, and LLMPirate for IP Piracy. We also provide details for four example course instances (GUIDE4ChipDesign, Build your ASIC, GUIDE4HardwareSecurity, and Hardware Design) that assemble GUIDE units into full semester offerings, learning outcomes, and capstone projects, all based on proven materials. For example, the GUIDE4HardwareSecurity course includes a project on LLM-aided hardware Trojan insertion that has been successfully deployed in the classroom and in Cybersecurity Games and Conference (CSAW), a student competition and academic conference for cybersecurity. We also organized an NYU Cognichip Hackathon, engaging students across 24 international teams in AI-assisted RTL design workflows. The GUIDE repository is open for contributions and available at: https://github.com/FCHXWH823/LLM4ChipDesign.
Figures & tables
Fig. 1: Educational approach for generative AI in chip design using the open-source GUIDE framework. Figure was generated using NotebookLM.
Topic
Subtopic
Unit
Description
LLM-aided RTL Generation
RTL Generation from NL
AutoChip [ 6 ]
Generate Verilog from a prompt and testbench plus iterative compilation/ simulation feedback.
ROME [ 7 ]
Uses hierarchical prompting to decompose complex designs so smaller open-source LLMs can generate larger Verilog systems with better quality and lower cost.
Veritas [ 8 ]
Has an LLM generate CNF clauses as a formal functional specification and deterministically converts CNF to Verilog for correctness by construction.
PrefixLLM [ 9 ]
Represents prefix-adder synthesis as structured text (SPCR) and performs iterative LLM-guided design space exploration to optimize area and delay.
VeriDispatcher [ 10 ]
Dispatch RTL tasks to LLMs using pre-inference difficulty prediction to improve quality and reduce LLM use cost.
Finetuned LLMs for RTL Generation
VGen [ 11 ]
Proposes a dedicated dataset and demonstrates that finetuning LLMs on this dataset significantly improves their Verilog code generation capabilities.
TABLE I: GUIDE taxonomy in our current repository: topics, subtopics, and representative units and descriptions.
Week
Theme
Typical Activities
1
Course setup
Course overview; GenAI for digital design; environment setup; first RTL-generation warm-up lab.