IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolution

Luanrong Chen; Renzhi Chen; Xinyu Li; Shanshan Li; Rui Gong; Lei Wang

cs.SEMar 26, 2026

IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolution

Authors: Luanrong Chen, Renzhi Chen, Xinyu Li, Shanshan Li, Rui Gong, Lei Wang

Organizations: National University of Defense Technology, Changsha, China · Defense Innovation Institute, Academy of Military Sciences, Beijing, China · Qiyuan Lab, Beijing, China

Abstract

Large language models (LLMs) have shown promise in generating RTL code from natural-language descriptions, but existing methods remain static and struggle to adapt to evolving design requirements, potentially causing structural drift and costly full regeneration. We propose IncreRTL, a LLM-driven framework for incremental RTL generation under requirement evolution. By constructing requirement-code traceability links to locate and regenerate affected code segments, IncreRTL achieves accurate and consistent updates. Evaluated on our newly constructed EvoRTL-Bench, IncreRTL demonstrates notable improvements in regeneration consistency and efficiency, advancing LLM-based RTL generation toward practical engineering deployment.

Figures & tables

Figure 1. Illustration of requirement-driven RTL updates. IncreRTL performs traceability-guided local regeneration, mitigating token and drift issues. Illustration showing requirement-driven modification in LLM-based RTL generation, including standard and evolved workflows.

Figure 2. Overview of the proposed IncreRTL framework. Overview diagram showing the architecture and workflow of IncreRTL.

Figure 3. Task template for incremental generation, where the LLMs generate only the impacted code snippets, ensuring unchanged line ranges and interfaces. Illustration showing requirement-driven modification in LLM-based RTL generation, including standard and evolved workflows.

Figure 4. Example of localized regeneration for AR1, where the requirement changes from full 32-bit output to exposing only the upper 24 bits; traceability links confine updates to Fragment 2, and IncreRTL regenerates only its output logic while keeping Fragment 1 unchanged. Illustration showing requirement-driven modification in LLM-based RTL generation, including standard and evolved workflows.

Magnitude	Category	Change Description	Count	Module
Minor	FunctionalBehaviorChange	Add an enable input and an output for detecting any edge	34	Edge Detector
	ControlConfigChange	Add an enable signal to pause/resume the counter	28	Counter
	InterfaceProtocolChange	Add a second independent address and data port for dual-read	8	ROM
	MicroArchitectureRefactor	Replace serial iteration with parallel array multiplication	20	Multiplier
Major	ModuleStructuralRefactor	Split arithmetic and logic units into separate submodules	22	ALU
Major	SystemInterfaceRefactor	Replace external interface with standard AXI bus protocol	8	Memory Controller

Table 1. Sample examples of different requirement change types and modules in EvoRTL-Bench , showing the magnitude and count for each type.

Method	Consistency	Relative Token	Syntax		Function
	Score	Usage	pass@5	pass@10	pass@5	pass@10
Direct	0.2684	-	78.15	80.03	56.30	60.00
Full	0.7337	1.8	89.17	90.01	67.67	70.33
Ours	0.8123	1.46	89.08	89.17	61.34	64.17

Table 2. Comparison of IncreRTL with Direct and Full baselines on the EvoRTL benchmark. The table reports Consistency Score (CS), Relative Token Usage (RTU), and syntactic and functional correctness (pass@k).

Magnitude	Category	Consistency	Syntax	Function
Minor	FunctionalBehaviorChange	0.7935	94.12	68.24
	ControlConfigChange	0.6846	89.66	62.07
	InterfaceProtocolChange	0.8109	71.43	42.85
	MicroArchitectureRefactor	0.7192	89.00	60.00
Major	ModuleStructuralRefactor	0.6142	78.26	44.35
Major	SystemInterfaceRefactor	0.7070	91.43	42.86

Table 3. Scalability of IncreRTL across different requirement change types on the EvoRTL benchmark.

Figure 5. Performance comparison between IncreRTL and Direct Generation across different large models. Illustration showing requirement-driven modification in LLM-based RTL generation, including standard and evolved workflows.

RTL Code Generation

Register-transfer-level (RTL) code generation turns hardware specifications into synthesizable circuits, balancing functional correctness with area, timing, and power.

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Large language models (LLMs) have facilitated impressive progress in software engineering, code generation, tooling, and systems. Concurrently, a significant body of research has developed which explores a growing variety of methods and systems for applying LLMs to hardware and chip design (e.g., systems for RTL code generation based on functional description). However, when it comes to open Verilog/RTL code-generation, we need high-quality training samples to build specialized and more effective LLM systems through fine-tuning or low-rank adaptation. Here, we propose a ``judge-renew-check-renew-check'' (JRCRC) pipeline which updates a current public dataset using a hierarchy of state-of-the-art commercial LLM models differing in their costs and capabilities in RTL code generation. This approach achieves a cost-effective mechanism for filtering and refining code-generation samples into a higher-quality training dataset. Our experiments also identify some common weaknesses of LLMs in rule-based reasoning and logic, and consequently, in RTL code-generation. Having identified these weaknesses, we develop an architecture for incorporating pre-processing tools to dynamically assist the LLMs in inferring logical relationships from tabular data formats. With our tools-assisted architecture for RTL code generation, we achieve significant overall performance gains in the VerilogEval benchmark and outperform many state-of-the-art methods. Our LLM4RTL system achieves performance comparable to that of GPT-4O using a significantly much smaller LLM.

Abstract

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