Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design

Agile hardware design flows are a critically needed force multiplier to meet the exploding demand for compute. Recently, agentic generative AI systems have demonstrated significant advances in algorithm design, improving code efficiency, and enabling discovery across scientific domains. Bridging these worlds, we present ArchAgent, an automated computer architecture discovery system built on AlphaEvolve. We show ArchAgent's ability to automatically design/implement state-of-the-art (SoTA) cache replacement policies (architecting new mechanisms/logic, not only changing parameters), broadly within the confines of an established cache replacement policy design competition. In two days without human intervention, ArchAgent generated a policy achieving a 5.3% IPC speedup improvement over the prior SoTA on public multi-core Google Workload Traces. On the heavily-explored single-core SPEC06 workloads, it generated a policy in just 18 days showing a 0.9% IPC speedup improvement over the existing SoTA (a similar "winning margin" as reported by the existing SoTA). ArchAgent achieved these gains 3-5x faster than prior human-developed SoTA policies. Agentic flows also enable "post-silicon hyperspecialization" where agents tune runtime-configurable parameters exposed in hardware policies to further align the policies with a specific workload (mix). Exploiting this, we demonstrate a 2.4% IPC speedup improvement over prior SoTA on SPEC06 workloads. Finally, we outline broader implications for computer architecture research in the era of agentic AI. For example, we demonstrate the phenomenon of "simulator escapes", where the agentic AI flow discovered and exploited a loophole in a popular microarchitectural simulator - a consequence of the fact that these research tools were designed for a (now past) world where they were exclusively operated by humans acting in good-faith.

Computer Architecture research has traditionally required the exploration of vast, highly complex design spaces through manual human effort. Large Language Models (LLMs) offer an opportunity to accelerate this process by enabling fast and automated implementation and testing of different architectural mechanisms and their combinations. We introduce Agentic Architect, a framework for agentic CPU microarchitectural design-space exploration and optimization. The Agentic Architect combines LLM-driven code evolution with cycle-accurate simulation and hardware cost modeling to explore performance, area, and power tradeoffs. Starting from a seed design, the LLM is prompted to explore the design space by implementing changes, guided by prior evaluation feedback. Each new design is compiled, simulated on training workloads, evaluated against the optimization objective, and constrained by area and power budgets. Its score and diagnostics update the candidate population and guide subsequent iterations. We evaluate the Agentic Architect framework across prefetching, cache replacement, and branch prediction. On 213 traces spanning five benchmark suites, its evolved prefetchers lead the evaluated L1D and L2 designs, delivering up to 6.7% and 2.6% additional speedup, respectively, over the strongest state-of-the-art design, while the best evolved cache replacement design improves over Mockingjay by up to 1.7%. Moreover, across 191 branch-prediction traces, the evolved branch predictor achieves 97.62% of TAGE-SC-L's geometric mean IPC at 10.58% of its area. Our analysis highlights the importance of seed selection, hardware constraints, and training workloads in shaping search outcomes. Overall, Agentic Architect establishes the first end-to-end framework for agentic CPU microarchitectural design optimization, opening a new direction for architecture research.

Hardware infrastructure is a critical bottleneck for LLM-driven circuit design, limiting what agents can express, compile, and iteratively refine within an agentic loop. To address this bottleneck, we introduce CKTLEAN, a typed hardware infrastructure embedded in Lean. It supports hardware description, compilation to SystemVerilog, and interactive type-checking and proof feedback through a persistent read-eval-print loop (REPL). On this foundation, we build CKTFORMALIZER, an agent framework for hardware generation, repair, optimization, and source-level equivalence proving. We evaluate structural correctness through compilation, functional correctness through RTL and gate-level simulation, and formal correctness through proofs relative to stated specifications. Across VerilogEval, RTLLM, ResBench, and CVDP, CKTFORMALIZER with CKTLEAN achieves compilation rates of 91.1%-99.4%. Among designs that pass RTL simulation, 95.4%-100.0% jointly complete synthesis and place-and-route and pass design-rule and layout-versus-schematic checks. In a separate evaluation on 30 VerilogEval problems, interactive proof-state feedback raises kernel-accepted equivalence proof completion from 53.3% to 63.3%. Hardware evaluation feedback also guides architecture exploration and iterative power, performance, and area (PPA) optimization, with synthesis-area reductions of up to 58.6% in the optimization loop. These results suggest that typed representations and explicit proof-state feedback help structure the agentic loop: compiler diagnostics guide targeted repairs, while proof-state feedback helps agents identify what remains to be proved and determine the next proof step. Project Page: https://ckt-formalizer.github.io/