TOPCELL: Topology Optimization of Standard Cell via LLMs

Zhan Song; Yu-Tung Liu; Chen Chen; Guoheng Sun; Jiaqi Yin; Chia-tung Ho; Ang Li; Haoxing Ren

cs.LGApr 15, 2026

TOPCELL: Topology Optimization of Standard Cell via LLMs

Authors: Zhan Song, Yu-Tung Liu, Chen Chen, Guoheng Sun, Jiaqi Yin, Chia-tung Ho, Ang Li, Haoxing Ren,

Organizations: University of Maryland College Park, USA · NVIDIA Santa Clara, CA, USA · NVIDIA Austin, TX, USA

Abstract

Transistor topology optimization is a critical step in standard cell design, directly dictating diffusion sharing efficiency and downstream routability. However, identifying optimal topologies remains a persistent bottleneck, as conventional exhaustive search methods become computationally intractable with increasing circuit complexity in advanced nodes. This paper introduces TOPCELL, a novel and scalable framework that reformulates high-dimensional topology exploration as a generative task using Large Language Models (LLMs). We employ Group Relative Policy Optimization (GRPO) to fine-tune the model, aligning its topology optimization strategy with logical (circuit) and spatial (layout) constraints. Experimental results within an industrial flow targeting an advanced 2nm technology node demonstrate that TOPCELL significantly outperforms foundation models in discovering routable, physically-aware topologies. When integrated into a state-of-the-art (SOTA) automation flow for a 7nm library generation task, TOPCELL exhibits robust zero-shot generalization and matches the layout quality of exhaustive solvers while achieving an 85.91x speedup.

Figures & tables

Figure 1. Comparison of 7

nm

AOI221_X1 layouts before (Top) and after (Bottom) topology optimization by TOPCELL . The optimized topology doesn’t require a dummy gate insertion, leading to a smaller area. This demonstrates the effectiveness of TOPCELL for improving cell layout quality.

Figure 2. The TOPCELL workflow, showing Data Preparation (Left) to build a topology-diverse dataset and a GNN model for routability reward, and the main process (Right), which includes GRPO Post-Training (Top) to update the LLM policy and Inference (Bottom) to optimize a given cell topology.

Figure 3. Structure of the Swap Region in LLM-Guided Topology Permutation. The region is bounded by NCA and NCD.

Name	PDA Congestion (Mean)	Routable Rate (%)
Baseline: SO3-Cell	N/A	N/A
Ours: TOPCELL -3B	4.06 -0.26(6.02%)	69.7 +14.1(25.4%)
Ours: TOPCELL -7B	3.90 -0.34(8.02%)	77.3 +24.3(45.8%)
Qwen2.5-Coder-3B	4.32	55.6
Qwen2.5-Coder-7B	4.24	53.0
Qwen2.5-Coder-32B	4.33	54.0

Table 1. Comparative analysis of model performance in the evaluation benchmark. The overall SOTA results are shown in bold . Numbers in red indicate the performance improvement of our fine-tuned TOPCELL models over the respective Qwen2.5-Coder base models.

Cell	# $I$	# $T$	SO3-Cell		TOPCELL
Cell	# $I$	# $T$	OTC $\downarrow$	Runtime (sec)	OTC $\downarrow$	$t_{LLM}$ (sec)	$t_{P\&R}$ (sec)	Runtime (sec)	Speedup ( $\times$ )
NAND4_X2	4	8	685	3258.875	685	1.843	187.744	189.587	17.19
NOR4_X2	4	8	685	10176.047	685	1.793	149.688	151.481	67.18
AOI211_X1	4	8	53	24.683	53	1.803	0.654	2.457	10.05
OAI211_X1	4	8	53	60.099	85	1.762	14.077	15.839	3.79
AOI22_X2	4	8	355	14733.220	355	1.710	1139.043	1140.753	12.92

Table 2. Comparison of layout quality and runtime between SO3-Cell and TOPCELL . TOPCELL generates optimized netlists in only a fraction of the time required by SO3-Cell, achieving comparable layout quality with an average speedup of 85.91

\times

Figure 4. Comparison of Routable Rate in the evaluation benchmark during training using GRPO and SFT. Solid markers denote peak performance for each method.

Topology Optimization

Topology optimization finds material layouts that meet performance and manufacturing constraints across engineering systems.

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EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models

Guanglei Zhou, Chen-Chia Chang, Yikang Shen, Jonathan Ku+4

Electrical and Computer Engineering, Duke University, Durham, USA · MIT-IBM Watson AI Lab, Cambridge, USA · IBM T. J. Watson Research Center, Yorktown Heights, USA

Large Language Model-Guided Optimization Electronic Design Automation

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Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands. Recent advances have applied sequence-to-sequence fine-tuning on pretrained language models to directly generate circuit topologies from user specifications in a single pass. However, these one-shot generation methods failed to generate complex circuits due to their exponentially growing search spaces and limited training datasets. In this paper, we present EXPLORE, a search-enhanced framework that integrates simulator-guided Monte Carlo Tree Search (MCTS) with transformer-based decoding to enable test-time scaling for analog topology generation. By leveraging language-model priors and bypassing high-confidence structural tokens, EXPLORE allocates expensive simulator budget primarily toward topology-altering decisions during search. On a 6-component benchmark at a tight tolerance of 0.01, EXPLORE raises the success rate from 12% for one-shot generation and 33% for a sampling-and-filter baseline to 65%, and lowers MSE by over 20% relative to sampling-and-filter under the same search budget. These results establish EXPLORE as the first framework to integrate structured test-time search with LM decoding for analog topology generation, and a practical step toward scaling LLM-driven design automation.

Abstract

Topology Optimization

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