Dynamic Multi-Criteria Bottleneck Severity Index (DMBSI) for Semiconductor Wafer Manufacturing: A Genetically Optimised Framework for Reentrant Production Systems
Authors: Mohammad Sharifur Rahman, Karl McCreadie, Saugat Bhattacharyya, M M Manjurul Islam, Cormac McAteer, Bryan John Baker, Nuala Parker, Girijesh Prasad
Wafer fabrication exhibits unique characteristics, including reentrant process flows, variable bottlenecks, and highly variable process conditions. In order to identify the most severe bottleneck at each moment in time for semiconductor wafer fabrication, this research presents the Dynamic Multi-Criteria Bottleneck Severity Index (DMBSI), a new, data-driven methodology for analysing multiple diagnostic signals of cycle time to changes in process parameters, and the impact of reworks on cycle time in order to generate an interpretable, unified measure of bottleneck severity. The experimental validation of DMBSI was conducted using Manufacturing Execution System (MES) logs collected from 22 wafer production lots at a commercial 200 mm wafer fabrication line operated by Seagate Technology. Using 5-fold cross-validation, the GA-optimised DMBSI achieves a Pearson correlation of r = 0.80 with observed cycle-time contributions, representing an 8.1% improvement over the expert heuristic baseline (r = 0.74) and substantially outperforming the Theory of Constraints (TOC; r = 0.60) and Value Stream Mapping (VSM; r = -0.30). Furthermore, the unique time-windowed component of DMBSI enabled the identification of temporal bottleneck migration patterns, which shifted from the dominant constraints associated with dielectric deposition steps in the early production windows to those associated with over- and under-inspection in the later production windows. The integrated what-if counterfactual analysis demonstrated that a 50% reduction in waiting time at the top-ranked bottleneck step would reduce the mean cycle time by 7.2%, with the top five bottleneck steps offering a combined potential reduction of approximately 19%.
Automated material handling systems in semiconductor fabs are operated by a material control system (MCS) that must schedule a relay route for every transport command online, before execution. This is a data-driven scheduling problem in which route cost is dominated in the upper tail by queueing at heterogeneous, partially observable relay equipment, so route selection requires estimating both delivery time and congestion risk at the decision moment. This paper proposes a transport-network-aware dynamic congestion representation (TN-DCR). Built on a static directed transport graph induced by historically observed relay segments, TN-DCR combines structural route priors, multi-window network-wide congestion context, route-level bottleneck exposure, and an inductive graph-aware route embedding, all constructed under a prediction-time-safety invariant that admits only information observed strictly before the prediction moment. The representation feeds separate queue- and transfer-time regressors and an ordinal multi-label classifier producing calibrated multi-threshold exceedance scores, with an empirical-Bayes stock-key residual correction reducing systematic queue-time underprediction. The predictions serve as costs in a risk-constrained route-scheduling rule that minimizes predicted delivery time subject to a bound on extreme-congestion probability, embedding the learned predictors within a lightweight operations-research decision model. In a controlled closed-loop evaluation, mean delivery time falls by 16.4% and internal resource waiting time by 22.6% while throughput remains essentially unchanged.
In semiconductor manufacturing, defect analysis is essential, but manual inspection cannot scale. However, existing automated inspection methods remain insufficient for root-cause analysis and process optimization. To this end, we present SePArate, a weakly supervised wafer defect segmentation method. SePArate enables pixel-level separation of patterns by leveraging only image-level annotations. It consists of a three-phase training: encoder pretraining, knowledge transfer to learn spatial cues, and training on synthetic mixed-defect data for accurate segmentation. Experiments demonstrate that SePArate outperforms the baselines.
Reliability qualification of advanced semiconductor devices requires sequential stress decisions that balance characterization objectives against multiple competing failure mechanisms. Current practice relies on static test plans derived from population-level acceleration models, which cannot adapt to per-unit variability or real-time degradation observations. This paper presents a closed-loop adaptive test planning framework that formulates reliability qualification as a partially observable sequential decision problem and solves it using Monte Carlo tree search for seed-action simulators (MCTS-SA) coupled with extended Kalman filter (EKF) belief-state estimation. The framework models stochastic, per-device variability in bias temperature instability (BTI), electromigration (EM), and time-dependent dielectric breakdown (TDDB), and treats stress selection as a constrained sequential optimization, i.e., to maximize the probability of successful degradation characterization while respecting catastrophic failure constraints. Under the experimental assumptions used here (discrete stress actions, proxy damage observability, and cumulative degradation without recovery), we believe this to be a novel application of tree-search-based adaptive test planning to multi-mechanism reliability qualification. Across 5,000 planning iterations, the characterization yield (CY) improves from 20% in the first 500 iterations to over 54% in the final 500, with 39% cumulative success, while the best successful test sequence terminates with EM and TDDB damage fractions DEM=0.564 and DTDDB=0.537, well within safety margins. These results demonstrate that sequential Bayesian planning can synthesize damage-aware test policies that significantly outperform non-adaptive strategies for reliability qualification under competing failure modes.