Robotic disassembly of end-of-life (EoL) products requires robots to accommodate product variation, follow prerequisite sequences, and approach components precisely for contact-rich manipulation. Supervised fine-tuning (SFT) provides a practical path for adaptation, but limited and costly disassembly data cannot capture the distribution shifts arising from changing environments and product uncertainties. The policy's own rollouts record its approach attempts, and human corrections demonstrate recovery from its errors, but turning these experiences into better policy performance remains challenging. We introduce PACER, a Process-Aware Correction and Evidence Reweighting framework that learns from these experiences through SFT, using progress toward the target and each trace's source and outcome to weight valid action chunks in the native supervised action loss. PACER trains one policy per weighting setting and selects one of the resulting policies through held-out validation. We evaluate PACER on UR5e motherboard disassembly across five component classes, where it achieves 87/100 successful approach-and-handoff trials on the held-out benchmark, compared with 54/100 for vanilla post-SFT.
Figures & tables
Figure 1: Compared with outcome-only filtering and reward-based adaptation, PACER uses outcome and safety annotations to determine imitation eligibility, then combines execution-process evidence with trace roles to assign bounded weights to valid action chunks in the native supervised action loss.
Figure 2: PACER converts autonomous rollouts, operator corrections, and supplementary clean demonstrations into a weighted native-loss training signal by checking imitation eligibility and weighting valid action chunks with process evidence.
Overall ( n=100 )
Per component ( n=20 )
Offline
Method
Success
95% CI (%)
RAM
Conn.
CPU
GPU
CPU fan
Jval
Initial SFT πθ0
12
[7.0,19.8]
7
0
0
5
0
0.7214
Vanilla post-SFT
54
[44.3,63.4]
12
5
3
20
14
0.7579
Uniform all-eligible
64
[54.2,72.7]
16
3
8
20
17
0.7648
Outcome only
11
[6.3,18.6]
0
0
0
10
1
0.7340
Clean only
24
[16.7,33.2]
0
0
9
8
7
0.7425
Table 1: Validation scores and held-out hardware success counts. Each method has 10 trials on each of two configurations per component, one close to the training distribution and one out of distribution. Brackets give marginal Wilson 95% confidence intervals for the overall success rate, in percent. Bold marks success-count column maxima.
Success counts
PACER gap
Policy
Mild
Strong
Overall
95% CI (%)
Δ (pp)
95% CI
n=50
n=50
n=100
PACER selected
43
29
72
[62.5,79.9]
Reference
—
Fixed weighting rules
Fixed geometry
35
16
51
[41.3,60.6]
+21
[13,29]
RW-like
33
18
51
[41.3,60.6]
+21
[12,30]
Table 2: Controlled OOD comparison. Each policy has 50 trials on each of two OOD configurations, with mild and strong shifts. Overall intervals are Wilson 95% CIs in percent. Differences are selected PACER minus each row with paired bootstrap 95% CIs. Bold marks success-count column maxima.
Appendix figures & tables19 assets
Supplementary material from the paper’s appendix.
Appendix
Component
Canonical prompt
CPU
Extract the CPU by unlocking the bracket first, then pick up the CPU and place it inside the blue area as a high-value component.
RAM
Extract the closest visible RAM stick and place it inside the blue area as a high-value component.
CPU fan
Extract the CPU fan and place it inside the yellow area as a low-value component.
Connector
Extract the closest visible connector and place it inside the yellow area as a low-value component.
GPU
Extract the graphics card and place it inside the green area, as it needs subsequent disassembly.
Appendix
Table 3: Canonical language prompts by component.
Figure 3: One post-training collection cycle, starting from the initial policy after supervised fine-tuning. A rollout ends in a non-success state (a–c), an operator correction is seeded from that state (d–e), the arm returns to home (f–g), and a supplementary clean demonstration is recorded for the same cell (h–j).
Component
Configs
Rollouts
Success
Partial
Wrong orientation or location
Wrong region or target
Excluded
RAM
7
70
7
3
6
54
0
Connector
7
70
2
25
23
20
0
CPU
7
70
4
8
6
52
0
GPU
7
70
31
37
2
0
0
CPU fan
7
70
11
6
12
41
0
Appendix
Table 4: Per-component outcome distribution of the 70 autonomous rollouts across the seven collection configurations, with the failure count split into its two labels.
Component
Correction rows
Supp. clean rows
All compiled train rows
RAM
301
480
1616
Connector
351
572
2019
CPU
348
587
1880
GPU
107
334
1698
CPU fan
269
364
1623
Total
1376
2337
8836
Appendix
Table 5: Post-training buffer composition as compiled training-row counts after action-chunk compilation. The compiled column counts all rows in the training split, including failure and excluded rows retained for audit, and positively weighted rows per method are reported in Table 9 .
Component
Clean
Correction
Auto success
Partial
Failure / excluded
RAM
73
46
0
73
29
Connector
78
73
0
22
72
CPU
85
45
0
12
115
GPU
116
69
0
50
176
CPU fan
45
52
0
11
86
Appendix
Table 6: Compiled validation rows by component and role. Clean, correction, auto_success, and partial rows form the positive-scoring set Vc+ , failure or excluded rows are audit-only, and the ranking pass of Table 8 scores a fixed planner-phase subset of these rows.
Candidate
βprog
βprox
βterm
βstop
γcorr
γpart
τ
wmax
rw_like
0.30
0.45
0.15
0.05
1.20
0.60
1.00
4.50
progress_heavy
0.55
0.20
0.15
0.05
1.20
0.60
1.00
4.50
hover_proximity_heavy
0.20
0.60
0.10
0.05
1.20
0.60
1.00
4.50
terminal_stop_heavy
0.20
0.25
0.35
0.15
1.20
0.60
1.00
4.50
correction_heavy
0.30
0.45
0.15
0.05
1.80
0.70
1.00
4.50
conservative
0.30
0.45
0.15
0.05
1.20
0.40
1.50
2.50
Appendix
Table 7: The eight predeclared weighting settings. The selected candidate emphasizes terminal-region and stop-signal evidence.
Candidate
Internal validation score
Selected
terminal_stop_heavy
0.770760
yes
hover_proximity_heavy
0.770343
no
correction_heavy
0.769622
no
rw_like
0.769558
no
balanced_low_clip
0.769395
no
conservative
0.769244
no
Appendix
Table 8: Candidate ranking by the component-balanced internal validation score Jval , computed over the same fixed 294-row planner-phase validation subset for every candidate.
Baseline
Rows used
Train
Horizons
Non-correction rows
Weight
Gate
Selected
πθ0 no post-train
none
0
0
0
none
no
no
Vanilla post-SFT
clean, correction
3713
37130
2337
1
no
no
Uniform all-eligible
all eligible
4613
46130
3237
1
yes
no
Outcome only
clean, auto_success
2662
26620
2662
1
yes
no
Clean only
supp. clean
2337
23370
2337
1
yes
no
Correction only
correction
1376
13760
0
1
yes
no
Appendix
Table 9: Baseline specifications. The gate column indicates the use of the PACER eligibility gate gi . The train column counts the number of positively weighted training rows, the horizons column sums the mask over those rows, and the non-correction rows column counts positively weighted training rows in the clean, auto_success, or partial roles.
Comparison
Difference
95% CI (pp)
PACER − vanilla post-SFT
33 pp
[14, 49]
PACER − uniform all-eligible
23 pp
[9, 40]
PACER − fixed geometry
8 pp
[3, 12]
Appendix
Table 10: Paired success-rate differences with descriptive component-cluster bootstrap 95 percent intervals over the five components.
Figure 4: Per-component held-out success rate over 20 trials per component. Error bars are 95% Wilson binomial confidence intervals. PACER matches or exceeds fixed geometry on every component.
Candidate
Overall
95% CI (%)
Setup 1
Setup 2
terminal_stop_heavy
74/100
[64.63,81.60]
44/50
30/50
progress_heavy
72/100
[62.51,79.86]
42/50
30/50
conservative
66/100
[56.28,74.54]
40/50
26/50
ram_connector_recovery
59/100
[49.20,68.13]
39/50
20/50
rw_like
59/100
[49.20,68.13]
36/50
23/50
hover_proximity_heavy
55/100
[45.24,64.39]
36/50
19/50
Appendix
Table 11: Overall and setup-level hardware success for the eight PACER candidates. Each candidate has 100 trials, with 50 per setup. Confidence intervals are marginal Wilson 95% intervals for the overall success rate. Bold marks success-count column maxima.
Candidate
RAM
Connector
CPU
GPU
CPU fan
Overall
terminal_stop_heavy
15/20
9/20
17/20
20/20
13/20
74/100
progress_heavy
15/20
6/20
14/20
18/20
19/20
72/100
conservative
10/20
6/20
15/20
19/20
16/20
66/100
ram_connector_recovery
12/20
4/20
15/20
13/20
15/20
59/100
rw_like
4/20
2/20
19/20
16/20
18/20
59/100
hover_proximity_heavy
3/20
7/20
19/20
12/20
14/20
55/100
Appendix
Table 12: Success counts by component pooled across the two hardware setups. Each component has 20 trials per candidate, for 100 trials overall. Bold marks success-count column maxima.
Candidate
RAM
Connector
CPU
GPU
CPU fan
Setup total
(a) Setup 1
terminal_stop_heavy
5/10
9/10
10/10
10/10
10/10
44/50
progress_heavy
7/10
6/10
10/10
9/10
10/10
42/50
conservative
4/10
6/10
10/10
10/10
10/10
40/50
ram_connector_recovery
6/10
3/10
10/10
10/10
10/10
39/50
rw_like
4/10
2/10
10/10
10/10
10/10
36/50
Appendix
Table 13: Success counts within each hardware setup. Component cells report successes out of 10 trials; each setup total is out of 50. Bold marks success-count column maxima within each setup.
Training run
Hardware success
95% CI (%)
Selected policy, seed 42
33/50
[52.2,77.6]
Selected policy, seed 43
35/50
[56.2,80.9]
Selected policy, seed 44
32/50
[50.1,75.9]
Geometry perturbation
38/50
[62.6,85.7]
Appendix
Table 14: Seed and geometry sensitivity, with 50 hardware trials per fit and Wilson 95% intervals.
Figure 5: Held-out comparison on the CPU fan task across five methods. The first five rows show the reference policy πθ0 , vanilla post-SFT, outcome-only, fixed geometry, and selected PACER, in that order. Red circles mark wrong-location or off-target endpoints, yellow triangles mark near-miss endpoints, and green boxes mark endpoints that reach the target region. The sixth row is a separate, unscored illustration of the fixed downstream skill executed from a reached handoff state.
Figure 6: Held-out comparison on the RAM task across five methods. Row order and endpoint markers are as in Figure 5 .
Figure 7: Held-out comparison on the connector block task across five methods. Row order and endpoint markers are as in Figure 5 .
Figure 8: Held-out comparison on the GPU task across five methods. Row order and endpoint markers are as in Figure 5 .
Figure 9: Held-out comparison on the CPU task across five methods. Row order and endpoint markers are as in Figure 5 .
J. Mike Walker ’66 Department of Mechanical Engineering, Texas A&M University, College Station, TX 77843, USA. · Zachry Department of Civil and Environmental Engineering, Texas A&M University, College Station, TX 77843, USA.