GNN-Guided Local Refinement for Efficient Layout Decomposition with DSA-MP

Yu Feng; Liyi Zhou; Haoyu Wang; Yiming Xu; Hao Geng; Shaozhi Deng; Ningsheng Xu; Shisheng Xiong

cs.AIOct 15, 2026

GNN-Guided Local Refinement for Efficient Layout Decomposition with DSA-MP

Authors: Yu Feng, Liyi Zhou, Haoyu Wang, Yiming Xu, Hao Geng, Shaozhi Deng, Ningsheng Xu, Shisheng Xiong

Organizations: Fudan University · ShanghaiTech University · Sun Yat-sen University

Abstract

Multiple patterning lithography (MPL) has been widely used to improve lithography resolution in advanced nodes, but it faces cost limits as feature sizes shrink. Directed self-assembly (DSA) offers a cost-effective complement, extending the resolution of optical lithography to sub-10 nm and beyond. Integrating DSA into MPL (DSA-MP) further enhances the resolution of contact/via patterning. Nevertheless, growing design complexity exposes the limits of existing decomposition methods, which struggle to balance solution quality and runtime, and neglect edge-to-edge spacing constraints of DSA templates, compromising manufacturability. To address these issues, we introduce a new conflict graph model capturing the previously overlooked constraints and develop a local refinement strategy powered by the graph neural network, enabling efficient and scalable layout decomposition. Experiments demonstrate that our method achieves higher solution quality with faster convergence than state-of-the-art methods, while maintaining robustness across layout scales, design styles, technology nodes, and varying mask counts.

Figures & tables

Figure 1. (a) Traditional flow: solve from scratch until optimal or timeout. (b) Leveraging features from the initial solving phase, our flow predicts vias for mask reassignment. The solver reassigns masks only for these vias, keeping all others fixed, significantly speeding up convergence.

Figure 2. (a) DSA process flow. (b) Feasible templates: by adjusting template size, vias with different pitches can be fabricated, but the grouping range is limited by the natural pitch $L_{0}$ of the BCP. Moreover, a minimum edge-to-edge spacing between templates is required to ensure stable patterning.

Figure 3. (a) Original layout. (b) Decomposition with triple patterning. (c) Decomposition with DSA-MP (The red solid line shows the lithography simulation result from S-litho). (d) Another decomposition with DSA-MP.

Figure 4. Transforming an ILP instance to a bipartite graph.

Figure 5. (a) Our graph model. It unifies lithography spacing and template-related conflicts as edge-to-edge constraints between templates. Each via can be manufactured by a single-hole template, while vias connected by a two-hole template edge may alternatively use the two-hole template. Template conflict hyperedges represent all possible template conflicts. (b) An example of a feasible mask and template assignment.

Figure 6. Illustration of three types of edge-to-edge template spacing conflicts, each with a representative

c_{i}

highlighted by the black dashed arrow. (a)

SC

: taking

c_{i}=(a,b)

as an example, a conflict between two single-hole templates. (b)

STC

: taking

c_{i}=(a,t_{1})

as an example, a conflict between single-hole template

a

and two-hole template

t_{1}

. (c)

TTC

: taking

c_{i}=(t_{1},t_{2})

as an example, a conflict between two-hole templates

t_{1}

and

t_{2}

Figure 7. Our proposed framework. (A) Synthetic layouts are generated based on design rules extracted from the ASAP7 PDK. A time-limited ILP solver produces an initial solution, and a constraint on the count of via changes is added to identify the minimal set of vias requiring reassignment, forming the Vias-to-Refine dataset. (B) The ILP formulation is represented as a bipartite graph, and solver-derived features initialize a GNN trained on the dataset from (A) to predict vias requiring reassignment. (C) For a test layout, a time-limited ILP solver provides an initial solution. Based on GNN-predicted probabilities, a subset of vias is sampled for reassignment, while others are fixed, and only the selected vias are re-optimized.

Benchmark	Original		EILP ( Lin and Jiang, 2019 )				DLXplus ( Lin and Jiang, 2019 )				Ours
Benchmark	via	edge	cn	tn	cost	time (s)	cn	tn	cost	time (s)	cn	tn	cost	time (s)
test1	3977	7140	103	137	104.37	268.63	261	128	262.28	104.44	103	145	104.45	105.94
test2	3807	6570	91	117	92.17	6655.68	220	98	220.98	85.18	91	120	92.20	50.09
test3	3795	6170	81	99	81.99	446.88	195	79	195.79	80.31	81	102	82.02	31.90
test4	12025	19882	265	314	268.14	11528.07	542	114	243.14	612.33	265	324	268.24	193.88
test5	5180	8587	127	110	128.10	76.65	265	112	266.12	189.71	127	113	128.13	84.02

Table 1. Comparison results of DSA with TPL on 7 nm synthetic layouts.

Benchmark	Original		EILP ( Lin and Jiang, 2019 )				DLXplus ( Lin and Jiang, 2019 )				Ours
Benchmark	via	edge	cn	tn	cost	time (s)	cn	tn	cost	time (s)	cn	tn	cost	time (s)
BOOM_test1	15608	24758	273	210	275.10	634.57	900	774	907.74	706.67	273	439	277.39	121.29
BOOM_test2	16729	26325	430	209	432.09	1551.12	1133	1003	1143.03	1012.96	432	598	437.98	96.59
BOOM_test3	11586	18492	266	116	267.16	305.98	747	522	752.22	107.73	268	360	271.60	58.88
BOOM_test4	31486	50113	918	377	921.77	4920.61	2177	1899	2195.99	2051.60	922	938	931.38	330.97
BOOM_test5	13540	21320	285	156	286.56	1176.25	881	782	888.82	538.01	285	427	289.27	76.72

Table 2. Comparison results of DSA with TPL on 7 nm BOOM core layouts

Benchmark	Original		EILP ( Lin and Jiang, 2019 )				DLXplus ( Lin and Jiang, 2019 )				Ours
Benchmark	via	edge	cn	tn	cost	time (s)	cn	tn	cost	time (s)	cn	tn	cost	time (s)
N5_test1	4328	8244	27	288	29.88	299.25	115	255	117.55	50.26	27	294	29.94	44.51
N5_test2	7829	14772	40	540	45.40	2035.96	181	515	186.15	409.49	41	545	46.45	55.33
N5_test3	7006	12840	40	442	44.42	1230.44	151	435	155.35	196.12	40	453	44.53	58.89
N5_test4	10268	19226	55	741	62.41	541.88	247	703	254.03	549.43	55	749	62.49	88.20
N5_test5	6671	12262	25	436	29.36	653.43	134	408	138.08	147.88	25	441	29.41	48.95

Table 3. Comparison results of DSA with QPL on 5 nm industrial layouts.

Benchmark	Original		EILP ( Lin and Jiang, 2019 )				DLXplus ( Lin and Jiang, 2019 )				Ours
Benchmark	via	edge	cn	tn	cost	time (s)	cn	tn	cost	time (s)	cn	tn	cost	time (s)
N5_test_11	5551	11120	TLE	TLE	TLE	TLE	161	403	165.03	122.05	34	526	39.26	57.51
test11	116215	206000	TLE	TLE	TLE	TLE	TLE	TLE	TLE	TLE	3622	3895	3660.95	4636.34
test12	206659	366628	TLE	TLE	TLE	TLE	TLE	TLE	TLE	TLE	6287	6421	6351.21	17265.78
BOOM_test11	221696	352602	TLE	TLE	TLE	TLE	TLE	TLE	TLE	TLE	6054	5572	6109.72	5856.67
BOOM_test12	667477	1056475	TLE	TLE	TLE	TLE	TLE	TLE	TLE	TLE	18315	18787	18502.87	49369.75

Table 4. Cases where some algorithms exceed the 20-hour time limit (“TLE”).

Panel of Figure 8 — Figure 8. Ablation study on solver-derived features.

Training Data	cn	tn	cost	time (s)
the BOOM core layouts	44.4	556.7	49.967	97.218
Synthetic layouts	39.5	527.8	44.778	103.085

Table 5. GNN performance on 5 nm industrial layouts with different training sets.

Panel of Figure 9 — Figure 9. Manufacturability comparison among no DSA (MPL only), prior conflict graph model, and our proposed conflict graph model.

Figure 10. Post-OPC lithography simulation results. Gray rectangles denote targets and colored contours represent simulated printed patterns on different masks. (a) Results obtained using the prior conflict graph model. (b) Results obtained using our proposed conflict graph model.

Semiconductor Manufacturing

Semiconductor manufacturing uses process engineering, metrology, and automation to make chips reliably, improve yield, and meet tight device requirements.

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Abstract

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