cs.LGOct 19, 2026

Learn the Interface, Not the Implementation: Output Representation Dominates Training Regime in LLM-Based RTL Generation

Authors: Siddharth Patel, Vikram Singh, Siddharth Savyasachi Malu, Rohit Singh

Organizations: Dept. of Electronics Engineering, Shiv Nadar Institution of Eminence, Delhi-NCR, India · STMicroelectronics, Greater Noida, India · AI Center of Excellence, Shiv Nadar Institution of Eminence, Delhi-NCR, India

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Abstract

Large-language-model register-transfer-level (RTL) generation has concentrated on how to train the model: fine-tuning, continued pre-training, and reinforcement learning from a verifier. We argue this is the second-order question. On a bounded, formally specifiable task of generating single-error-correcting, double-error-detecting (SECDED) ECC memory wrappers, we hold the task, data, and correctness oracle fixed and vary two axes independently: the training regime (seven settings) and the output representation (four levels, from fully expanded flat Verilog to an eight-field configuration expanded by a deterministic generator). Because a reference generator exists, correctness is decided by formal equivalence over a design space of approximately ten million points, rather than sampled from a hand-written testbench. Two results follow. First, representation dominates: every representation close to raw RTL reaches a pass rate of at most 0.17, while the configuration reaches 0.83 with no training at all. Once the model emits the configuration, every training regime achieves a pass rate between 0.89 and 1.00. Second, raw RTL hits a hard output-length limit: a 512-bit design requires 44,237 tokens of flat Verilog compared with just 69 tokens for the configuration. Consequently, raw generation becomes infeasible above 32-bit data words rather than merely inaccurate. A model trained from scratch with fewer than 50 million parameters, combined with the verified generator, achieves 0.89 formal equivalence, compared with 1.00 for a 32-billion-parameter fine-tuned model, while using approximately 1600 times less inference energy per correct design. Inference energy also dominates amortized training energy. The lesson is to learn the interface, not the implementation.

Figures & tables

Fig. 1: The pipeline and the representation ladder. A natural-language spec or configuration enters the LLM front-end, which emits one of four output representations—shown with their 512-bit token counts. Only the configuration (L cfg ) is expanded by a deterministic generator; the raw, parameterised, and parity-matrix forms are emitted as implementation and checked directly against the reference by a five-level oracle (L0–L5), then shipped or refused. The two longest representations exceed a practical single-response generation budget—the output-length wall.
LevelOutputTokensBack-end
L rawflat expanded Verilog≈\approx 44,237none
L paramparameterised, generate loops≈\approx 4,029none
L hmatrixparity matrix + wrapper opts≈\approx 1,161matrix expander
L cfg8-field configuration69full generator
TABLE I: The four output representations (512-bit design).
Regime \\backslash Repr.L rawL paramL hmatrixL cfg
few-shot0.170.170.170.83
nn-copy———0.00
RAG———1.00
LoRA-SFT——0.00 †1.00
full-SFT———0.975
CPT-SFT———1.00
TABLE II: Pass rate by regime ×\times representation, scored by L3 formal equivalence to the reference (in-distribution). “—”: intentionally not run (Sec. V ).
Fig. 2: Pass rate versus generation length, per width. Truncation is shown distinct from incorrect RTL. Flat L raw generation is feasible only up to 32-bit words and hits the wall at 48 bits (4,096-token budget).
Method (L cfg )PassJ/designJ/correct
from-scratch ( << 50M)0.8870.440.50
MoE zero-shot0.36341947
dense QLoRA1.00814814
dense zero-shot0.449502,159
TABLE III: Joules per correct design ( == J/design ÷\div pass rate). All rows are GPU-isolated (per-GPU NVML energy counter, idle-subtracted, n=3n{=}3 , GPU energy only); clocks unpinned (Sec. VII ).
Fig. 3: Formal-equivalence rate versus energy per correct design (log xx -axis); bubble size is parameter count, colour is representation. All points are GPU-isolated (NVML counter, idle-subtracted, unpinned) except RAG, a provisional shared-box measurement (flagged in the plot). The from-scratch configuration model occupies the high-accuracy, low-energy corner—the specification-compression result made visual.
RegimeID (deploy)OOD widthOOD comboillegal refusal
RAG1.000.8870.931.00
LoRA-SFT1.001.001.001.00
CPT-SFT1.001.001.001.00
verifier-RL1.000.9750.951.00
from-scratch0.8870.6621.000.59
TABLE IV: Out-of-distribution behaviour (L cfg ); config-exact, except the last column (refusal accuracy on illegal specifications: fraction not silently legalized).
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