EGGPlacer: Energy-Guided Generative Chip Placement with Diffusion Models

Qi Zhou; Guojun Liu; Juanhong Zhao; Guangzhi Qi; Zehao Chen; Ming Lu

cs.AROct 22, 2026

EGGPlacer: Energy-Guided Generative Chip Placement with Diffusion Models

Authors: Qi Zhou, Guojun Liu, Juanhong Zhao, Guangzhi Qi, Zehao Chen, Ming Lu

Organizations: Faculty of Computing, Harbin Institute of Technology

Abstract

Chip placement strongly affects routed wirelength and thermal behavior, yet these downstream metrics are difficult to evaluate during macro placement. Learning-based macro placers commonly optimize the macro-only half-perimeter wirelength (HPWL), denoted mHPWL, which ignores standard cell connectivity and spatial demand. In contrast, analytical mixed-size placers optimize differentiable full netlist wirelength and density objectives but are typically unaware of thermal effects. We propose EGGPlacer, an energy-guided diffusion framework that incorporates analytical placement feedback and thermal feedback into macro placement generation. An analytical placer acts as an online physical response model, exposing the standard cell distribution and a full netlist wirelength proxy induced by each intermediate macro placement, while a differentiable thermal model provides temperature feedback. These signals are formulated as composable energies and injected throughout reverse diffusion without retraining the underlying generative model. Experiments on public placement benchmarks show that EGGPlacer achieves competitive mixed-size HPWL relative to strong analytical and learning-based macro placers. In the end-to-end evaluation, EGGPlacer also obtains the lowest average routed wirelength and peak temperature among the evaluated methods. Ablation studies further demonstrate that analytical and thermal guidance provide distinct and complementary benefits across wirelength proxies, routed wirelength, and thermal objectives.

Figures & tables

Figure 1: Routed wirelength (Routed WL), peak temperature (Peak T), and runtime for EGGPlacer and the evaluated baselines. Lower values on both axes are better, and larger circles indicate lower runtime.

Figure 2: Motivation for EGGPlacer. Learning-based macro placers primarily optimize mHPWL and omit standard cell contributions and thermal behavior. Analytical mixed-size placers optimize a full netlist wirelength proxy and density but remain unaware of thermal effects. EGGPlacer injects analytical and thermal energies into reverse diffusion to optimize wirelength and temperature.

Figure 3: An example chip placement. Green blocks denote macros, pink blocks denote standard cells, and colored boxes bound the pins included for each net.

Method	mHPWL		$\text{HPWL}_{\text{DP}}$
Method	Mean	Rank	Mean	Rank
DP	1.46	3.75	5.64	1.65
EffPlace + DP	1.00	1.55	6.69	4.20
ChipDiff + DP	0.90	1.53	6.89	4.16
RollPlace + DP	1.74	5.10	6.05	2.95
FlowPlace + DP	1.68	3.85	6.82	4.65

Table 1: Mixed-size placement summary across 20 benchmarks. The macro-only proxy mHPWL and the DREAMPlace-refined proxy

\text{HPWL}_{\text{DP}}

are reported in units of

10^{8}

and

10^{9}

, respectively. DP, EffPlace, and ChipDiff denote DREAMPlace, EfficientPlace, and ChipDiffusion, respectively. EGGPlacer values are arithmetic means over three random seeds. Lower is better.

Runtime (s)	DP	EffPlace	ChipDiff	RollPlace	FlowPlace	EGGPlacer
Macro Placement	–	769.66	128.29	8802.57	6.40	79.14
Mixed-Size Placement	19.73	18.66	18.51	16.06	17.88	16.26
Total	19.73	788.32	146.80	8818.63	24.28	95.40

Table 2: Average runtime across 20 benchmarks. DP, EffPlace, and ChipDiff denote DREAMPlace, EfficientPlace, and ChipDiffusion, respectively. Mixed-size placement refers to the DP refinement stage. EGGPlacer runtimes are averaged over three random seeds.

Method	$\text{HPWL}_{\text{ORFS}}$		Routed WL		Peak T
Method	Mean	Rank	Mean	Rank	Mean	Rank
DP	4.31	3.40	5.48	3.25	62.93	3.55
EffPlace	4.88	4.40	5.86	4.40	65.38	5.30
ChipDiff	4.86	4.53	5.85	4.53	62.35	3.11
RollPlace	4.21	3.05	5.10	3.10	63.18	3.40
FlowPlace	4.40	2.95	5.26	2.85	63.63	3.70

Table 3: End-to-end summary across 20 benchmarks.

\text{HPWL}_{\text{ORFS}}

and routed wirelength are reported in

10^{6}\,\mu\mathrm{m}

and peak temperature in

{}^{\circ}\mathrm{C}

. DP, EffPlace, and ChipDiff denote DREAMPlace, EfficientPlace, and ChipDiffusion, respectively. EGGPlacer values are arithmetic means over three random seeds, while external baselines report single runs. Lower is better.

Panel of Figure 4 — Figure 4: Ablation of analytical and thermal guidance. Means over three seeds are normalized per benchmark to EGGPlacer w/o A&T. Lower is better. Benchmark indices from 1 to 20 correspond, respectively, to ariane133, ariane136, ariane81, bp, bp68, bp_be, bp_be12, bp_fe, bp_fe38, bp_multi, bp_multi57, dft68, ethernet, isa_npu, mor1kx, or1200, swerv_wrapper, swerv_wrapper43, vga_lcd, and VeriGPU. Peak temperature is normalized as the rise above $318.15\,\mathrm{K}$ ( $45\,^{\circ}\mathrm{C}$ ). Markers denote benchmarks, solid lines connect each variant’s results, and dashed lines denote variant means.

Placement metric	Spearman $\rho$ (95% CI)	Rank agreement
$\text{HPWL}_{\text{DP}}$	$0.660$ $[0.405,0.842]$	$72.5\%$
$\text{HPWL}_{\text{ORFS}}$	$0.918$ $[0.817,0.977]$	$91.7\%$

Table 4: Fidelity of HPWL across placement engines for 80 observations covering all combinations of variants and designs. Each observation is averaged over three random seeds and normalized within its design. Rank agreement with routed wirelength compares pairwise orderings.

Appendix figures & tables12 assets

Supplementary material from the paper’s appendix.

Appendix

Variant	mHPWL	$\text{HPWL}_{\text{DP}}$	Routed WL	Peak T	P95 T
w/o A&T	1.07 (1.000)	6.67 (1.000)	5.47 (1.000)	61.89 (1.000)	61.22 (1.000)
w/o A	1.26 (1.159)	6.93 (1.027)	5.40 (0.998)	61.19 (0.960)	60.56 (0.958)
w/o T	1.53 (1.424)	5.90 (0.922)	4.94 (0.940)	61.77 (0.994)	61.12 (0.994)
EGGPlacer	1.71 (1.550)	6.08 (0.949)	4.99 (0.958)	61.50 (0.980)	60.86 (0.981)

Appendix

Table 5: Summary of the four energy guidance variants over 20 benchmarks. Each metric is first averaged over three random seeds for every benchmark and variant. Each entry reports the arithmetic mean, followed in parentheses by the mean ratio to the unguided w/o A&T variant across benchmarks. mHPWL,

\text{HPWL}_{\text{DP}}

, and Routed WL are reported in units of

10^{8}

10^{9}

, and

10^{6}\,\mu\mathrm{m}

, respectively. mHPWL and

\text{HPWL}_{\text{DP}}

are proxies, whereas Routed WL is measured after ORFS routing. Temperature ratios are computed from the temperature rise above the

318.15\,\mathrm{K}

(

45\,^{\circ}\mathrm{C}

) ambient temperature. All temperature values are measured by HotSpot rather than estimated by the thermal surrogate and are reported in

{}^{\circ}\mathrm{C}

Panel of Figure 5 — Figure 5: Additional ablation results for analytical and thermal guidance. Means over three seeds are normalized per benchmark to EGGPlacer w/o A&T. Lower is better. Benchmark indices use the mapping defined in Figure 4 . P95 temperature is normalized as the rise above $318.15\,\mathrm{K}$ ( $45\,^{\circ}\mathrm{C}$ ). Markers denote benchmarks, solid lines connect each variant’s results, and dashed lines denote variant means.

Panel of Figure 6 — Figure 6: Correlations within each design between wirelength proxies and routed wirelength. Each marker denotes the mean over three seeds for a variant and benchmark after log normalization by the geometric mean across the four EGGPlacer variants for that benchmark. The analysis contains four variants and all 20 benchmarks (80 observations). Dashed lines are pooled linear fits for visualization. Spearman confidence intervals are obtained from 10,000 bootstrap samples that resample complete benchmarks.

Relation	Pearson $r$	Spearman $\rho$ (95% CI)	Mean design $\rho$	Rank agreement
DP vs. ORFS	0.861	0.684 $[0.433,0.856]$	0.560	74.2%
DP vs. RWL	0.787	0.660 $[0.405,0.842]$	0.520	72.5%
ORFS vs. RWL	0.941	0.918 $[0.817,0.977]$	0.880	91.7%

Appendix

Table 6: Engine dependence of placement proxy fidelity to routed wirelength. DP and ORFS denote

\text{HPWL}_{\text{DP}}

and

\text{HPWL}_{\text{ORFS}}

, respectively, and RWL denotes final routed wirelength. Correlations use 80 observations, each averaged over three seeds and normalized within its design. Confidence intervals resample complete benchmarks.

Panel of Figure 7 — Figure 7: Calibration of the thermal surrogate on the four EGGPlacer ablation variants. Panels (a) and (b) show signed errors averaged over three seeds for individual benchmarks. Panels (c) and (d) compare temperature changes predicted by the surrogate with those measured by HotSpot after enabling thermal guidance. Here, $\Delta T=T_{\mathrm{enabled}}-T_{\mathrm{disabled}}$ , where $T_{\mathrm{enabled}}$ and $T_{\mathrm{disabled}}$ are temperatures from otherwise identical variants with thermal guidance enabled and disabled, respectively. Negative values indicate improvement. “T $\mid$ A” and “T $\mid$ no A” denote comparisons with and without analytical guidance, respectively. Crosses denote means, and the dashed diagonal denotes ideal agreement.

Figure 8: ORFS global placement results obtained with macro locations generated by six placement methods on four representative designs. Red rectangles denote macros, blue points denote standard cells, and green points denote terminals.

Figure 9: HotSpot temperature distributions at steady state for the placements in Figure 8 . Red stars and blue triangles mark the hottest and coolest locations, respectively. Each design uses a common temperature scale across methods, shown below its column.

Benchmark	DP	EffPlace	ChipDiff	RollPlace	FlowPlace	EGGPlacer
ariane133	2.98	2.53	2.18	3.90	5.37	3.98 $\pm$ 0.09
ariane136	3.95	2.56	2.27	5.00	5.51	4.50 $\pm$ 0.31
ariane81	3.38	2.47	2.17	4.99	4.90	5.35 $\pm$ 0.34
bp	0.48	0.32	0.35	0.81	0.47	0.72 $\pm$ 0.16
bp68	0.88	0.59	0.58	1.63	0.86	1.42 $\pm$ 0.25
bp_be	0.35	0.21	0.27	0.28	0.24	0.42 $\pm$ 0.04

Appendix

Table 7: mHPWL results for each design (

10^{8}

). sw and sw43 abbreviate swerv_wrapper and swerv_wrapper43. EGGPlacer reports means over three seeds

\pm

sample standard deviations. Bold and underlined values rank first and second.

Benchmark	DP	EffPlace	ChipDiff	RollPlace	FlowPlace	EGGPlacer
ariane133	6.85	7.55	7.13	7.49	7.98	7.36 $\pm$ 0.08
ariane136	7.46	7.91	8.23	7.84	8.15	7.81 $\pm$ 0.10
ariane81	7.18	8.62	7.86	7.77	8.08	7.87 $\pm$ 0.10
bp	9.71	11.62	12.25	10.72	10.83	11.00 $\pm$ 0.14
bp68	16.61	26.85	26.04	19.60	30.27	20.51 $\pm$ 1.13
bp_be	4.60	4.72	4.91	4.72	4.80	4.89 $\pm$ 0.04

Appendix

Table 8:

\text{HPWL}_{\text{DP}}

results for each design after DREAMPlace refinement (

10^{9}

). sw and sw43 abbreviate swerv_wrapper and swerv_wrapper43. Other conventions follow Table 7 .

Benchmark	DP	EffPlace	ChipDiff	RollPlace	FlowPlace	EGGPlacer
ariane133	7.02	7.54	7.39	7.73	7.54	7.29 $\pm$ 0.27
ariane136	7.14	7.79	7.89	7.39	8.04	7.30 $\pm$ 0.14
ariane81	6.64	8.42	7.39	6.47	6.45	6.66 $\pm$ 0.40
bp	10.54	11.94	10.18	9.59	9.39	10.32 $\pm$ 0.43
bp68	20.09	22.32	16.79	13.94	19.09	12.97 $\pm$ 0.58
bp_be	4.24	4.19	4.77	4.00	4.32	4.32 $\pm$ 0.23

Appendix

Table 9: Routed wirelength results for each design (

10^{6}\,\mu\mathrm{m}

). sw and sw43 abbreviate swerv_wrapper and swerv_wrapper43. EGGPlacer reports means over three seeds

\pm

sample standard deviations. Baselines are single runs. Bold and underlined values rank first and second.

Benchmark	DP	EffPlace	ChipDiff	RollPlace	FlowPlace	EGGPlacer
ariane133	54.28	54.50	52.32	52.53	53.74	51.99 $\pm$ 0.14
ariane136	54.54	53.92	52.62	54.96	53.74	52.39 $\pm$ 0.60
ariane81	56.11	58.44	60.19	56.07	58.08	55.53 $\pm$ 0.34
bp	55.38	56.92	54.82	53.75	55.08	54.40 $\pm$ 0.45
bp68	75.07	86.41	75.74	73.00	77.66	69.45 $\pm$ 0.75
bp_be	63.44	63.55	61.88	62.15	61.62	60.95 $\pm$ 0.80

Appendix

Table 10: HotSpot peak temperature results for each design (

{}^{\circ}\mathrm{C}

). sw and sw43 abbreviate swerv_wrapper and swerv_wrapper43. Other conventions follow Table 9 .

Design	Variant	mHPWL	HPWL DP	HPWL ORFS	Routed WL	Peak T	P95 T
ariane133	w/o A&T	2.807	7.750	6.732	7.936	51.88	51.65
	w/o A	3.424	7.532	6.291	7.458	51.27	50.94
	w/o T	3.791	7.266	6.148	7.315	51.90	51.69
	EGGPlacer	3.978	7.361	6.130	7.294	51.99	51.63
ariane136	w/o A&T	2.890	8.556	6.993	8.249	52.32	52.09
	w/o A	3.374	8.428	6.226	7.424	51.76	51.46

Appendix

Table 11: Results for the four energy guidance variants on each design, averaged over three seeds. mHPWL and

\text{HPWL}_{\text{DP}}

are reported in units of

10^{8}

and

10^{9}

, respectively, while

\text{HPWL}_{\text{ORFS}}

and routed wirelength are reported in units of

10^{6}\,\mu\mathrm{m}

. Peak and p95 temperatures are measured by HotSpot and reported in

{}^{\circ}\mathrm{C}

. sw and sw43 denote swerv_wrapper and swerv_wrapper43.

Electronic Design Automation

Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.

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Jul 19, 2026

CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models

Analytical placers rely on differentiable objective functions to guide placement, typically combining intermediate surrogate metrics such as half-perimeter wirelength (HPWL) and cell-density penalties. However, these placement-stage surrogates remain misaligned with downstream routed and timing quality. Prior work reduces this gap with human-designed terms or learned black-box surrogates, but the former requires expert retuning and the latter is difficult to explain, debug, or deploy in analytical placement flows. CoEvoP&R addresses these limitations with a large language model (LLM)-based framework that automatically evolves analytical placement objectives. At each generation, the prompt combines the restricted objective interface, baseline context, and archived prior candidates with routing-related feedback from placement, timing proxy, and routing tools. The LLM proposes readable differentiable objectives, which are embedded and validated in DREAMPlace, evaluated through a timing proxy and an actual router, and stored with their feedback to guide later generations. Across eight ChiP-Bench Nangate45 designs and three seeds, CoEvoP&R reduces post-route routed wirelength and congestion by 16.9% and 36.7%, with gains of 0.70 ns in worst negative slack and a 912 ns reduction in total negative slack magnitude over native DREAMPlace. Across eight ICCAD 2015 Superblue designs, it reduces post-route routed wirelength and congestion by 5.4% and 23.2%. Code is available at https://github.com/FCHXWH823/CoEvoP-R.git.

Ruogu Chen, Weihua Xiao, Ramesh Karri +1

University of Alberta Edmonton, Alberta, Canada · New York University New York, New York, United States

Automated Heuristic Design Large Language Model-Guided Optimization Electronic Design Automation

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Apr 26, 2026

FlowPlace: Flow Matching for Chip Placement

Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for pre-training, require long sampling times, and often result in overlaps due to their dependence on gradient-based solvers during the sampling process. To overcome these issues, we propose FlowPlace, which features mask-guided synthetic data generation, flow-based efficient training with flexible prior injection, and hard constraint sampling for overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks show FlowPlace achieves better PPA metrics, 10-50

\times

faster sampling efficiency, and zero overlaps.

Peng Xie, Ke Xue, Yunqi Shi +6

1State Key Laboratory of Novel Software Technology, Nanjing University, China · School of Artificial Intelligence, Nanjing University, China · 3Huawei Noah’s Ark Lab, China

Constrained Generative Modeling Flow Matching Electronic Design Automation Generative Modeling Flow-Based Generative Modeling

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Aug 13, 2026

PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization

Macro placement significantly affects a chip's post-route performance, power, and area (PPA). Most placement methods optimize half-perimeter wirelength (HPWL) as the primary objective. However, recent benchmarking shows a near-zero correlation between HPWL and post-route timing metrics such as the worst negative slack (WNS) and total negative slack (TNS). As a result, all six evaluated artificial intelligence (AI) placers degraded PPA relative to the hierarchical baseline. Recent efforts have tried to train cross-stage predictors to close this gap. However, existing methods focus on macro-only representations and use pre-route metrics as training labels. A label fidelity study of ten circuits at four design flow stages reveals that HPWL and pre-route timing poorly reflect final post-route timing rankings. In contrast, post-global-routing achieves the best balance between final timing fidelity and label generation cost-effectiveness. Based on this finding, PPAPlace is a timing-driven differentiable surrogate predicting post-route PPA from macro and standard-cell placements. The surrogate is a dual-stream predictor that combines graph attention over the chip netlist with spatial convolution over the placement grid. It is trained on post-global-routing labels. The predicted WNS and TNS gradients flow end-to-end back to cell coordinates. PPAPlace exploits these gradients in two ways: as a co-objective injected into an analytical placer's optimization loop (PPAPlace-CoOpt), and as a post-placement refinement step that adjusts macro positions via projected gradient descent (PPAPlace-Refine). On five ChiPBench test circuits excluded from training, PPAPlace improves average WNS and TNS by 22% and 51% over the hierarchical baseline while preserving power and routability, using the same predictor without test-circuit retraining. Code is available at https://github.com/ValleyC/PPAPlace.

Ruogu Chen, Jie Han

University of Alberta Department of Electrical and Computer Engineering Edmonton, AB, Canada

Macro Placement Electronic Design Automation Surrogate Modeling Differentiable Optimization

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Abstract

Electronic Design Automation

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