Hardware-Matched Spiking Neural Networks for Real-Time Purkinje Cell Spike Classification
Authors: Arooba Farhan, Afsah Syed, Muhammad Fahd Ibrahim Bhatti, Muhammad Areeb Khalid Kidwai, Muhammad Ahsan Salar Khan, Vincenzo Romano, Muhammad Ali Siddiqi
Organizations: Electrical Engineering Department, Lahore University of Management Sciences, Pakistan · Department of Neuroscience, Erasmus University Medical Center, Rotterdam, The Netherlands
Distinguishing Purkinje cell (PC) simple spikes (SSs) from complex spikes (CSs) is key to studying cerebellar function. PC recordings commonly rely on wired headstages, whose tethers restrict natural movement in freely behaving animals. Untethered headstages remove this constraint, but cannot continuously transmit raw recordings within their power budgets, making on-headstage spike classification an attractive form of compression, provided it runs accurately in real time on constrained hardware. This work presents two compact spiking neural networks (SNNs) matched to their target hardware: ConvSNN, which maps to the Matrix Vector Processor (MVP) of an EFM32PG28 microcontroller, and StreamSNN, which processes one waveform value per timestep using learned time constants and fixed synaptic delays for a dedicated SKY130 circuit. Evaluated on cells unseen during training, ConvSNN achieves a CS F1 of 0.873 with 1,018 parameters and StreamSNN 0.837 with 527 parameters, both with eight-bit weights. On the microcontroller, MVP acceleration reduces ConvSNN latency by 62.3% and extends estimated battery life to 33.73hours on a 50mAh battery. In SKY130, StreamSNN occupies 0.173mm2 and consumes 0.46μJ per event, with 0.2ms of computation within an 8.3ms end-to-end latency.
Figures & tables
Fig. 1: Overview of the proposed system. (A) Conventional wired setup, in which a mouse with a Mini-Amp-64 headstage records PC activity through an amplifier, filter, and ADC. (B) Extracellular PC recording containing simple spikes (SSs) and complex spikes (CSs). (C) On-device spike detection and classification. (D) Output stored as sample index and spike type instead of raw data. (E) The two SNN classifiers: ConvSNN processes the full 57-value window as a fixed input over eight timesteps, while StreamSNN processes one waveform value per timestep through LIF neurons with learned time constants, fixed synaptic delays, and adaptive-threshold (ALIF) neurons.
Fig. 2: NEO-based spike detection and waveform extraction. Each detection defines a window spanning 30 samples before and 197 samples after the trough, reduced to 57 input values by four-sample averaging. Right: Functional mapping of ConvSNN onto the EFM32PG28 Cortex-M33 and MVP.
Work
Model
Params
Size
SS
CS
FP
Cell-held-out a
Ours
ConvSNN
1,018
1,041 B
.958
.873
.911
Ours
StreamSNN
527
687 B
.950
.837
.894
Random split, 40/20/40
[ 10 ]
SNet-4 int8
2,500
2.5 kB
.965
.867
–
[ 10 ]
SNet-4 float
2,500
–
.970
.890
–
TABLE I: Classification F1 of proposed and prior classifiers.
Fig. 3: Per-recording F1 scores of ConvSNN and StreamSNN across 64 PCs under cell-held-out evaluation.
Spiking neural networks process information through discrete, time-dependent neural events, aiming for efficient computation and biologically inspired learning.
Implantable brain-computer interfaces require on-node spike sorting to reduce telemetry bandwidth and power while maintaining reliable neural decoding. This paper presents a hardware-oriented deep binarized neural network (DBNN) spike-sorting system with two binarized hidden layers with 256 neurons and a fixed-point output layer to enable multiplier-free inference dominated by sign-controlled accumulation and bit-wise logic. The proposed classifier operates on compact 16-sample spike waveforms to reduce the implementation cost (16-256-256-3) and achieves a median classification accuracy of 98.7% on both synthetic and in-vivo datasets. An FPGA prototype on a Cyclone V device operates at 50 MHz and requires 528 cycles per spike, corresponding to a 0.01 ms compute latency, while consuming 828 ALMs and 1023 registers with zero DSP blocks. For ASIC feasibility, the DBNN is implemented using FreePDK45-based flow; synthesis in Synopsys Design Compiler indicates an estimated silicon area of 0.014 mm2 and an operating power of 122 nW at 20 kHz under a 1.1 V supply. These results demonstrate that the proposed DBNN spike sorter offers a favorable trade-off between accuracy and implementation cost, supporting low-power, implantable neural interfaces. Overall, the proposed DBNN spike sorter achieves high accuracy (98.7%) with extremely low hardware cost (0.014 mm2, 122 nW at 20 kHz) and multiplier-free operation, making it suitable for low-power, implantable neural interfaces. This paper introduces the first DBNN designed for real-time neural spike sorting, striking an excellent balance between input data size and network complexity.
Binyi Ren, Luca M. Meyer, Majid Zamani
The School of Electronics and Computer Science (ECS), University of Southampton, Southampton SO17 1BJ, U.K.
We introduce mlx-snn, the first spiking neural network (SNN) library built natively on Apple's MLX framework. As SNN research grows rapidly, all major libraries -- snnTorch, Norse, SpikingJelly, Lava -- target PyTorch or custom backends, leaving Apple Silicon users without a native option. mlx-snn provides six neuron models (LIF, IF, Izhikevich, Adaptive LIF, Synaptic, Alpha), four surrogate gradient functions, four spike encoding methods (including an EEG-specific encoder), and a complete backpropagation-through-time training pipeline. The library leverages MLX's unified memory architecture, lazy evaluation, and composable function transforms (mx.grad, mx.compile) to enable efficient SNN research on Apple Silicon hardware. We validate mlx-snn on MNIST digit classification across five hyperparameter configurations and three backends, achieving up to 97.28% accuracy with 2.0--2.5 times faster training and 3--10 times lower GPU memory than snnTorch on the same M3 Max hardware. mlx-snn is open-source under the MIT license and available on PyPI. https://github.com/D-ST-Sword/mlx-snn
Spiking Neural Networks (SNNs) are promising for energy-efficient spatiotemporal pattern recognition at the edge, but efficient deployment and on-device adaptation require specialized hardware. In this work, we present an FPGA implementation of multilayer SNNs for spatiotemporal pattern classification, in which both inference and training take place on the same hardware. Our design adopts a temporal-forward-only training algorithm that avoids the memory and latency overhead associated with traditional Backpropagation Through Time (BPTT). A mixed-precision scheme balances training stability with resource efficiency, and architectural optimization maximizes hardware and memory utilization. We further identify and resolve hazards that arise when inference and learning share the same memory, including port conflicts between the forward and backward access patterns and read-after-write dependencies in floating-point potential accumulation. Experimental evaluations on MNIST and five multivariate time-series classification datasets demonstrate that, with fully on-chip training, our SNN model achieves accuracy comparable to SNN or LSTM trained with BPTT. Compared to CPU and GPU based implementations, our FPGA design delivers 2.5 to 6 times higher throughput while consuming an order of magnitude less energy per sample.
Jingang Jin, Yue Ma, Zhenhang Zhang +1
Department of Electrical Engineering and Computer Science Syracuse University, Syracuse, New York, USA