Hardware-Matched Spiking Neural Networks for Real-Time Purkinje Cell Spike Classification

Arooba Farhan; Afsah Syed; Muhammad Fahd Ibrahim Bhatti; Muhammad Areeb Khalid Kidwai; Muhammad Ahsan Salar Khan; Vincenzo Romano; Muhammad Ali Siddiqi

cs.AROct 27, 2026

Hardware-Matched Spiking Neural Networks for Real-Time Purkinje Cell Spike Classification

Authors: Arooba Farhan, Afsah Syed, Muhammad Fahd Ibrahim Bhatti, Muhammad Areeb Khalid Kidwai, Muhammad Ahsan Salar Khan, Vincenzo Romano, Muhammad Ali Siddiqi

Organizations: Electrical Engineering Department, Lahore University of Management Sciences, Pakistan · Department of Neuroscience, Erasmus University Medical Center, Rotterdam, The Netherlands

Abstract

Distinguishing Purkinje cell (PC) simple spikes (SSs) from complex spikes (CSs) is key to studying cerebellar function. PC recordings commonly rely on wired headstages, whose tethers restrict natural movement in freely behaving animals. Untethered headstages remove this constraint, but cannot continuously transmit raw recordings within their power budgets, making on-headstage spike classification an attractive form of compression, provided it runs accurately in real time on constrained hardware. This work presents two compact spiking neural networks (SNNs) matched to their target hardware: ConvSNN, which maps to the Matrix Vector Processor (MVP) of an EFM32PG28 microcontroller, and StreamSNN, which processes one waveform value per timestep using learned time constants and fixed synaptic delays for a dedicated SKY130 circuit. Evaluated on cells unseen during training, ConvSNN achieves a CS F1 of 0.873 with 1,018 parameters and StreamSNN 0.837 with 527 parameters, both with eight-bit weights. On the microcontroller, MVP acceleration reduces ConvSNN latency by 62.3% and extends estimated battery life to 33.73~~hours on a 50~~mAh battery. In SKY130, StreamSNN occupies 0.173~~mm $^2$ and consumes 0.46~~ $μ$ J per event, with 0.2~~ms of computation within an 8.3~~ms end-to-end latency.

Figures & tables

Fig. 1: Overview of the proposed system. (A) Conventional wired setup, in which a mouse with a Mini-Amp-64 headstage records PC activity through an amplifier, filter, and ADC. (B) Extracellular PC recording containing simple spikes (SSs) and complex spikes (CSs). (C) On-device spike detection and classification. (D) Output stored as sample index and spike type instead of raw data. (E) The two SNN classifiers: ConvSNN processes the full 57-value window as a fixed input over eight timesteps, while StreamSNN processes one waveform value per timestep through LIF neurons with learned time constants, fixed synaptic delays, and adaptive-threshold (ALIF) neurons.

Fig. 2: NEO-based spike detection and waveform extraction. Each detection defines a window spanning 30 samples before and 197 samples after the trough, reduced to 57 input values by four-sample averaging. Right: Functional mapping of ConvSNN onto the EFM32PG28 Cortex-M33 and MVP.

Work	Model	Params	Size	SS	CS	FP
Cell-held-out a
Ours	ConvSNN	1,018	1,041 B	.958	.873	.911
Ours	StreamSNN	527	687 B	.950	.837	.894
Random split, 40/20/40
[ 10 ]	SNet-4 int8	2,500	2.5 kB	.965	.867	–
[ 10 ]	SNet-4 float	2,500	–	.970	.890	–

TABLE I: Classification F1 of proposed and prior classifiers.

Fig. 3: Per-recording F1 scores of ConvSNN and StreamSNN across 64 PCs under cell-held-out evaluation.

Freq. (MHz)	With MVP			Without MVP
	$I_{\mathrm{avg}}$ (mA)	$t_{\mathrm{inf}}$ (ms)	$E_{1}$ ( $\mu$ J)	$I_{\mathrm{avg}}$ (mA)	$t_{\mathrm{inf}}$ (ms)	$E_{1}$ ( $\mu$ J)
13	0.83	5.620	15.440	0.85	14.557	40.957
16	0.92	4.566	13.904	0.95	11.828	37.194
19	1.01	3.845	12.854	1.04	9.9603	34.287
26	1.20	2.810	11.257	1.24	7.279	29.876
32	1.37	2.283	10.456	1.42	5.914	27.797

TABLE II: Spike-Classification Performance With/Without MVP

Fig. 4: Estimated battery life for the complete head-stage using battery capacities of 12, 25, and 50 mAh.

Metric	Classifier	Detector	Whole chip
Area (mm 2 )	0.173	0.047	1.59
Power (mW)	2.30	1.49	15.95
Latency (ms)	0.20	0.16	8.31
Energy per event ( $\mu$ J)	0.46	–	3.20
Energy per sample (nJ)	–	61	–

TABLE III: ASIC results in SKY130 at a 100 ns clock period.

Spiking Neural Networks

Spiking neural networks process information through discrete, time-dependent neural events, aiming for efficient computation and biologically inspired learning.

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DBNN: Neural Spike Classification Using a Deep Binarized Neural Network

Binyi Ren, Luca M. Meyer, Majid Zamani

The School of Electronics and Computer Science (ECS), University of Southampton, Southampton SO17 1BJ, U.K.

Efficient Neural Network Inference Brain-Computer Interfaces Binary Neural Networks

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Implantable brain-computer interfaces require on-node spike sorting to reduce telemetry bandwidth and power while maintaining reliable neural decoding. This paper presents a hardware-oriented deep binarized neural network (DBNN) spike-sorting system with two binarized hidden layers with 256 neurons and a fixed-point output layer to enable multiplier-free inference dominated by sign-controlled accumulation and bit-wise logic. The proposed classifier operates on compact 16-sample spike waveforms to reduce the implementation cost (16-256-256-3) and achieves a median classification accuracy of 98.7% on both synthetic and in-vivo datasets. An FPGA prototype on a Cyclone V device operates at 50 MHz and requires 528 cycles per spike, corresponding to a 0.01 ms compute latency, while consuming 828 ALMs and 1023 registers with zero DSP blocks. For ASIC feasibility, the DBNN is implemented using FreePDK45-based flow; synthesis in Synopsys Design Compiler indicates an estimated silicon area of 0.014 mm2 and an operating power of 122 nW at 20 kHz under a 1.1 V supply. These results demonstrate that the proposed DBNN spike sorter offers a favorable trade-off between accuracy and implementation cost, supporting low-power, implantable neural interfaces. Overall, the proposed DBNN spike sorter achieves high accuracy (98.7%) with extremely low hardware cost (0.014 mm2, 122 nW at 20 kHz) and multiplier-free operation, making it suitable for low-power, implantable neural interfaces. This paper introduces the first DBNN designed for real-time neural spike sorting, striking an excellent balance between input data size and network complexity.

Abstract

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