OPERA: OPamp Design by an Expert-Taught Reasoning Agent, from Specifications to Layout

Vishal Saxena; Soumyajit Mandal

cs.AROct 29, 2026

OPERA: OPamp Design by an Expert-Taught Reasoning Agent, from Specifications to Layout

Authors: Vishal Saxena, Soumyajit Mandal

Organizations: ECE Dept., University of Delaware Newark, DE, USA · Instr. Div., Brookhaven National Laboratory Upton, NY, USA

Abstract

Analog flows from specifications to a signed-off layout rarely run without manual iteration. Recent large language model (LLM) agents size circuits with optimizer loops over the device dimensions and stop at the schematic. We present OPERA (OPamp design by an Expert-taught Reasoning Agent), in which a general-purpose LLM agent designs CMOS opamps from specifications to post-layout sign-off with open-source tools. First, the designer teaches the agent the gm/ID method: map the specifications to transconductances and minimum currents, choose gm/ID per device role from characterized lookup tables, and size from equations, leaving a few knobs to search and an explainable design. Second, the agent learns the gLayout framework and taught layout practice, and writes a reusable layout generator that closes the layout and extraction loop at designer-approved gates. In SKY130, the agent designed a shared constant-gm bias and six opamps (5T, folded-cascode and telescopic OTAs; Miller, folded-cascode and telescopic two-stage) for fun >= 50 MHz, PM >= 60 degrees, SR 25 V/μs into 1 pF and a minimum dc gain of 30 to 60 dB. All six layouts are DRC-clean and LVS-matched, and their extracted netlists meet every target at all 15 PVT corners ( fun >= 53.7 MHz, PM >= 62.1 degrees, SR >= 27.9 V/μs). The benchmark netlists are released at https://github.com/AMPICLab/AMPICBench.

Figures & tables

Fig. 1: The OPERA flow. (1) The designer gives the specifications, teaches skills and decides at the gates. (2) A general-purpose LLM agent applies the taught skills and (3) sizes the circuit with the six-step

g_{m}/I_{D}

flow (specifications to

g_{m}

and minimum currents, per-role

g_{m}/I_{D}

L

, sizing from tables, checks, trade-offs), leaving a few knobs. (4) Simulation over 15 PVT corners returns worst-corner feedback to those knobs. (5) The layout generator builds the cell after the unit and floorplan gates, and (6) DRC in two decks, LVS, extraction and post-layout PVT simulation sign it off or trigger regeneration. (7) Each signed-off cell is distilled into a reusable, tested generator that the next opamp reuses.

Skill	Taught by the designer	Used by the agent as
Topology	Signal path, gain and pole nodes, stack headroom, replica bias, folding currents	Headroom budget per stack
$\mathbf{g_{m}/I_{D}}$	Six-step flow: specs to $g_{m}$ and currents, $g_{m}/I_{D}$ per role, $L$ , size, check, explore	Density, $f_{T}$ , $g_{m}r_{o}$ from tables; sizes from equations; worst-corner knob iteration
Compensation	Two-stage Miller recipe: $m=g_{m2}/g_{m1}$ , $C_{c}$ , $R_{z}$ placement	Starting $C_{c}$ , $R_{z}$ , $m$ ; one knob per specification
Layout	Floorplans; common centroid, interdigitation, dummies; rings per stage; packing $\geq$ 70%; short parasitics sensitive nodes	Generator templates; matching and packing checkers

TABLE I: Skills Taught by the Designer

Work	Topo.	Size b	$\mathbf{g_{m}}$ / $\mathbf{I_{D}}$	Comp.	PVT	Layout	Sign- off c	Reus. gen.	Taught skills
AnalogCoder [ 1 ]	✓	L	✗	✗	✗	✗	✗	✗	✗
ADO-LLM [ 10 ]	✗	O	✗	✗	✗	✗	✗	✗	✗
LEDRO [ 12 ]	✗	O	✗	✗	✗	✗	✗	✗	✗
AutoSizer [ 13 ]	✗	O	✗	✗	✗	✗	✗	✗	✗
Artisan [ 22 ]	✓	E	✓	$\circ$	✗	✗	✗	✗	✗
AmpAgent [ 4 ]	$\circ$	E	✗	$\circ$	✗	✗	✗	✗	✗

TABLE II: Comparison with LLM-Based Analog Design Flows. ✓ Yes,

\circ

Partly, ✗ No.

Panel of Figure 4 — Fig. 2: Two-stage opamp with a folded-cascode first stage and a class-A second stage, designed by OPERA. (a) Schematic drawn by the agent from its sized netlist, devices colored by role; labels are finger counts. (b) Its automatically generated layout; DRC/LVS clean and meets specs in all corners.

	Circuit	Knobs a	$\mathbf{A_{0}}$ (dB)	$\mathbf{f_{un}}$ (MHz)	PM ( ∘ )	SR b (V/ $\mu$ s)	I ${}_{\text{DD}}$ ( $\mu$ A)
S1	5T OTA	$n$	31.1–31.8	68.1–76.0	82.4–84.1	35.4	126–144
S1	FC OTA	$n_{1},n_{2}$	51.1–53.0	66.5–77.4	67.6–72.6	33.2	282–358
S1	Telescopic	$n$	51.9–55.0	96.6–115.2	71.2–77.9	41.4	243–307
S2	Miller	$n,m,C_{c},R_{z}$	60.8–64.0	82.2–100.8	69.1–75.7	46.1	338–422
S2	FC 2-stage	$n,m,C_{c},R_{z}$	63.2–68.2	57.5–72.8	70.2–78.9	28.6	330–424
S2	Tele. 2-stage	$n,m,C_{c},R_{z}$	68.7–78.0	75.5–95.8	66.8–75.6	27.1	330–423

TABLE III: Opamp Results over 15 PVT Corners (Schematic,

C_{L}

=1 pF, VDD=1.8 V,

V_{CM}

=0.9 V, On-Chip Bias)

		OPERA a	Protocol A (spec)		Protocol B (sat.)
	Circuit	A / B	Random	TPE	Random	TPE
S1	5T OTA	54 / 54	5/5 (58)	5/5 (48)	5/5 (76)	5/5 (48)
S1	FC OTA	30 / 59	3/3 (250)	3/3 (129)	1/3 (368)	1/3 (32)
S1	Telescopic	30 / 59	3/3 (35)	3/3 (45)	2/3 (258)	2/3 (41)
S2	Miller	30 / 53	3/3 (40)	3/3 (204)	3/3 (40)	2/3 (181)
S2	FC 2-stage	30 / 55	2/3 (281)	3/3 (141)	0/3	0/3

TABLE IV: Runs to First Passing Design: Passing Seeds (Median Runs)

	Cell	Area ( $\mu$ m 2 )	Util.	DRC a LVS	$\mathbf{A_{0}}$ (dB) PEX	PM ( ∘ ) PEX	$\mathbf{f_{un}}$ (MHz) PEX	SR (V/ $\mu$ s)
S1	5T OTA	496	89.2%	0/0 ✓	31.1–31.8	81.8–83.5	66.5–74.3	34.3
S1	FC OTA	3482	69.0%	0/0 ✓	51.0–53.0	63.5–68.6	63.5–74.0	31.5
S1	Telescopic	3015	86.8%	0/0 ✓	51.9–54.9	66.2–72.9	92.4–109.9	41.4
S2	Miller	2356	78.3%	0/0 ✓	60.8–64.0	64.6–71.0	78.8–95.6	46.1
S2	FC 2-stage c	3570	66.9%	0/0 ✓	63.2–68.3	62.1–70.7	53.7–68.0	27.9
S2	Tele. 2-stage	2893	57.3%	0/0 ✓	68.5–78.0	63.1–72.7	71.1–89.5	30.5

TABLE V: Layouts and Post-Layout Results (SKY130, Extracted R and C, Ideal

R_{z}

and

C_{c}

, 15 Corners)

Electronic Design Automation

Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.

See all 219 papers

AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models
Aug 13, 2026Mohammed Ayman Habib, Rylan Hart, Morteza FayaziMulti-Agent LLM Systems Electronic Design Automation
University of Utah, Salt Lake City, Utah, USA
A Self-Calibrating Framework for Analog Circuit Sizing Using LLM-Derived Analytical Equations
Apr 8, 2026Antonio J. Bujana, Aydin I. KarsilayanElectronic Design Automation Analog Circuit Sizing
Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA. · Department of Engineering, Benedictine College, Atchison, KS, USA.
AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing
Sep 22, 2026Yijia Hao, Pratibha Verma, Dongxu Guo +4Large Language Model-Guided Optimization Electronic Design Automation
Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, UK · Department of Electrical Engineering, Indian Institute of Technology Indore, India · School of Informatics, The University of Edinburgh, UK +1

Aug 13, 2026J/K move · Enter open · S save

AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models

Mohammed Ayman Habib, Rylan Hart, Morteza Fayazi

University of Utah, Salt Lake City, Utah, USA

Multi-Agent LLM Systems Electronic Design Automation Analog Circuit Sizing

Open paper AskPDF arXiv

Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition. Among recent developments, LLMs have introduced a promising approach by bringing natural language reasoning to circuit design tasks. The majority of conventional LLM-based approaches provide fragmented solutions that focus either only on sizing or topology generation. These methods require adding specific technical knowledge manually, which is inefficient and prone to hallucinations during circuit sizing. Moreover, the inherent trade-off in meeting different specs makes current approaches iterative and tedious. Another shortcoming is the inability to create innovative topologies, which may lead to sub-optimal designs due to reliance on conventional topologies. In this paper, we present AaLLM, an open-source end-to-end multi-agent LLM workflow that takes user specs as input and outputs the appropriate netlist, encompassing both topology generation and circuit sizing. AaLLM automates the creation of a relevant knowledge base from research papers and textbooks to combat tedious manual data collection. A RAG model is implemented to emulate circuit design expertise using this knowledge base. Moreover, AaLLM uses a novel tri-agent feedback system comprising a Designer that determines circuit component values, a Critic that scrutinizes these values, and an Evaluator that minimizes circuit sizing iterations by arbitrating between the other two agents. AaLLM-generated novel topologies achieve a figure of merit (FoM) comparable to that of known topologies, and up to 3x higher for certain circuits. Testing on several circuit topologies, our results show a 3x - 4.5x decrease in the number of SPICE calls at inference when compared to SOTA multi-agent LLM pipelines. The results also show a 40x decrease in wall-clock time compared to existing approaches.

Abstract

Electronic Design Automation

Explore similar work

AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models

A Self-Calibrating Framework for Analog Circuit Sizing Using LLM-Derived Analytical Equations

AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing