Large language models offer a promising route to register-transfer-level (RTL) design, but reliable implementations require checking and revision based on electronic design automation (EDA) tools' feedback. Existing RTL-specialized models often lack learned interaction with such EDA tools or rely on separate generation and repair components. We introduce RTL-Interact, a multi-task post-training framework that trains a single RTL-specialized model to generate RTL, construct task-appropriate EDA checks, and revise implementations using tool feedback. The framework combines automatically constructed multi-task demonstrations with staged supervision from chain-of-thought to tool-integrated reasoning. We further introduce Pattern-Aware Policy Optimization (PAPO) for multi-task reinforcement learning. PAPO augments Group Relative Policy Optimization with correctness-gated rewards that favor concise successful checking while rewarding effective revision, and uses task grouping to preserve coverage across objectives. On CVDP, RTL-Interact-32B achieves 48.7% weighted Pass@1 and 68.9% Pass@5, surpassing its teacher model, DeepSeek-V3.2, while RTL-Interact-8B achieves 44.9% weighted Pass@1. Additionally, we show that PAPO can reduce average tool calls by 63.8% while improving Pass@1. Both models also outperform all RTL-specialized baselines on VerilogEval v2 and RTLLM v2, demonstrating the effectiveness of our method.
Figures & tables
Figure 1: Representative solution processes of (a) RTL generation models, such as RTL-Coder ( Liu et al., 2023b ) ; (b) RTL reasoning models, such as CodeV-R1 ( Zhu et al., 2025 ) ; and (c) our EDA-interactive RTL model.
Figure 2: Overview of RTL-Interact : (a) multi-task TIR data construction and RL task selection starting from the CoT dataset; (b) CoT-to-TIR staged supervision; and (c) PAPO with pattern-aware trajectory rewards and task grouping. Reward bars are schematic; incorrect final RTL receives zero reward.
Table 2: CVDP non-agentic code-generation results (%). Entries are Pass@1/Pass@5; Overall is weighted by category size. Size denotes total model parameters; – indicates undisclosed size. Tool marks whether EDA tools are available. Best and second-best results for each metric are shown in bold and underlined , respectively; ties share the same formatting. † marks the tool-using distillation teacher; ChipMATE uses its V+P cross-verification workflow.
Table 3: VerilogEval v2 and RTLLM v2 results (%). CC and SR denote code completion and specification-to-RTL. Tools indicate EDA-tool availability. Size denotes total model parameters. Best and second-best results in each metric are bold and underlined ; ties at displayed precision share formatting. † marks the distillation teacher.
Figure 3: RL training dynamics for 8B and 32B. Pale solid lines show the series before smoothing.
Appendix figures & tables2 assets
Supplementary material from the paper’s appendix.
Appendix
Figure 6
Figure 5: Measured endpoint changes in the separate 8B generation-only run. Segments connect SFT and RL results within a category; they are not training-time curves. Labels show Pass@1 gains in percentage points (pp). This run has a different SFT initialization from the full multi-task run.
State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, China · University of Chinese Academy of Sciences, China · Peking University, China +1
1SKLP, Institute of Computing Technology, Chinese Academy of Sciences · University of the Chinese Academy of Sciences · School of Advanced Interdisciplinary Sciences