Large language models offer a promising route to register-transfer-level (RTL) design, but reliable implementations require checking and revision based on electronic design automation (EDA) tools' feedback. Existing RTL-specialized models often lack learned interaction with such EDA tools or rely on separate generation and repair components. We introduce RTL-Interact, a multi-task post-training framework that trains a single RTL-specialized model to generate RTL, construct task-appropriate EDA checks, and revise implementations using tool feedback. The framework combines automatically constructed multi-task demonstrations with staged supervision from chain-of-thought to tool-integrated reasoning. We further introduce Pattern-Aware Policy Optimization (PAPO) for multi-task reinforcement learning. PAPO augments Group Relative Policy Optimization with correctness-gated rewards that favor concise successful checking while rewarding effective revision, and uses task grouping to preserve coverage across objectives. On CVDP, RTL-Interact-32B achieves 48.7% weighted Pass@1 and 68.9% Pass@5, surpassing its teacher model, DeepSeek-V3.2, while RTL-Interact-8B achieves 44.9% weighted Pass@1. Additionally, we show that PAPO can reduce average tool calls by 63.8% while improving Pass@1. Both models also outperform all RTL-specialized baselines on VerilogEval v2 and RTLLM v2, demonstrating the effectiveness of our method.
Figures & tables
Figure 1: Representative solution processes of (a) RTL generation models, such as RTL-Coder ( Liu et al., 2023b ) ; (b) RTL reasoning models, such as CodeV-R1 ( Zhu et al., 2025 ) ; and (c) our EDA-interactive RTL model.
Figure 2: Overview of RTL-Interact : (a) multi-task TIR data construction and RL task selection starting from the CoT dataset; (b) CoT-to-TIR staged supervision; and (c) PAPO with pattern-aware trajectory rewards and task grouping. Reward bars are schematic; incorrect final RTL receives zero reward.
Table 2: CVDP non-agentic code-generation results (%). Entries are Pass@1/Pass@5; Overall is weighted by category size. Size denotes total model parameters; – indicates undisclosed size. Tool marks whether EDA tools are available. Best and second-best results for each metric are shown in bold and underlined , respectively; ties share the same formatting. † marks the tool-using distillation teacher; ChipMATE uses its V+P cross-verification workflow.
Table 3: VerilogEval v2 and RTLLM v2 results (%). CC and SR denote code completion and specification-to-RTL. Tools indicate EDA-tool availability. Size denotes total model parameters. Best and second-best results in each metric are bold and underlined ; ties at displayed precision share formatting. † marks the distillation teacher.
Figure 3: RL training dynamics for 8B and 32B. Pale solid lines show the series before smoothing.
Appendix figures & tables2 assets
Supplementary material from the paper’s appendix.
Appendix
Figure 6
Figure 5: Measured endpoint changes in the separate 8B generation-only run. Segments connect SFT and RL results within a category; they are not training-time curves. Labels show Pass@1 gains in percentage points (pp). This run has a different SFT initialization from the full multi-task run.
Register Transfer Level (RTL) design translates high-level specifications into hardware using HDLs such as Verilog. Although LLM-based RTL generation is promising, the scarcity of functionally verifiable high-quality data limits both accuracy and diversity. Existing post-training typically produces a single HDL implementation per specification, lacking awareness of RTL variations needed for different design goals. We propose RTLSeek, a post-training paradigm that applies rule-based Diversity-Oriented Reinforcement Learning to improve RTL correctness and diversity. Our Diversity-Centric Multi-Objective Reward Scheduling integrates expert knowledge with EDA feedback, and a three-stage framework maximizes the utility of limited data. Experiments on the RTLLM benchmark show that RTLSeek surpasses prior methods, with ablation results confirming that encouraging broader design-space exploration improves RTL quality and achieves the principle of "the more generated, the better results." Implementation framework, including the dataset, source code, and model weights, is shown at https://anonymous.4open.science/r/DAC2026ID71-ACB4/.
Xinyu Zhang, Zhiteng Chao, Yonghao Wang +6
State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, China · University of Chinese Academy of Sciences, China · Peking University, China +1
Large language models (LLMs) have shown increasing promise in generating functionally correct register-transfer-level (RTL) hardware designs. Recent systems improve further through EDA-integrated reinforcement learning with syntax, simulation, and PPA rewards, but train a general RTL generator before deployment while test-time approaches search with a frozen policy. We instead perform reinforcement learning at test time, allowing the LLM policy to adapt to executable EDA feedback for the specific RTL problem at hand. We propose TTT-RTL, to our knowledge the first per-design test-time training framework that closes the loop between an LLM policy and an EDA pipeline for RTL optimization. TTT-RTL samples candidate implementations, verifies them through syntax checking and simulation, scores valid designs using synthesis-derived PPA product, reuses high-reward variants through a PUCT-indexed design-state pool, and updates the policy with an entropic policy-gradient objective. To stabilize policy updates under sparse or plateaued rewards, we introduce an adaptive KL-budget controller that adjusts the entropy constraint using reference KL, effective sample size, and reward saturation signals. On RTLLM v2.0 under Nangate 45nm, TTT-RTL reduces the geometric-mean PPA product by 65.1% over the reference, outperforming the strongest published frozen-policy agent baseline at 26.1%. On an industrial XuanTie C910 FPU leading-zero-anticipation unit under Sky130, TTT-RTL achieves a 59.4% ADP reduction, and ablations confirm that policy adaptation, state reuse, and KL-budget control each contribute. These results suggest that test-time training with executable EDA feedback can move LLM-based RTL generation beyond functional correctness toward physically optimized hardware.
Peilong Zhou, Zhirong Chen, Cangyuan Li +4
1SKLP, Institute of Computing Technology, Chinese Academy of Sciences · University of the Chinese Academy of Sciences · School of Advanced Interdisciplinary Sciences
Large language models (LLMs) have shown strong promise in specification-to-RTL generation. Among the explorations, the self-correction paradigm has significantly advanced LLM-based RTL generation. However, two challenges limit further progress. Existing benchmarks are saturated by advanced LLMs, leaving little room to evaluate the agentic self-correction framework. The monolithic self-correction paradigm rewrites the entire design at once, where LLMs are susceptible to error confusion and corruption of originally correct code. To address the benchmark challenge, we contribute ScaleBench, a more challenging benchmark of 200 complex RTL designs. To address the challenge in methodology, we propose CorrectRTL, an agentic framework that realizes a new decompose-then-correct paradigm, in which the LLM agent explicitly decouples scaffold construction from detailed implementation. CorrectRTL contributes three core techniques: (1)Structure-oriented decomposition, (2)Snippet-based RAG, and (3)~SVA-based self-correction. On ScaleBench, CorrectRTL improves Pass@1 from 20.5% to 49.0% (+28.5%). On VerilogEval, CorrectRTL achieves up to 96.1% Pass@1, demonstrating consistent improvements across both simple and complex designs.
Jing Wang, Shang Liu, Hangan Zhou +4
Hong Kong University of Science and Technology Clear Water Bay, Hong Kong