SpikeAD: Toward Multiplication-Free Spike-Controlled Neuromorphic Architecture for Energy-Efficient Small Object Detection

Zhifan Song; Haralampos-G. Stratigopoulos

cs.NEOct 28, 2026

SpikeAD: Toward Multiplication-Free Spike-Controlled Neuromorphic Architecture for Energy-Efficient Small Object Detection

Authors: Zhifan Song, Haralampos-G. Stratigopoulos

Organizations: Sorbonne University, CNRS, LIP6, Paris, France

Abstract

Energy-constrained aerial platforms require accurate object detection under strict power and latency budgets, yet conventional inference remains bottlenecked by multiply-accumulate (MAC) operations. While spiking neural networks (SNNs) offer bio-inspired efficiency, many SNN detectors retain hybrid MACs in intermediate layers, or use spike-driven inference where multi-level spikes are interpreted as repeated binary events. We propose SpikeAD, a direct-trained spike-controlled neuromorphic aerial detector. In SpikeAD, sparse bounded integer spikes act strictly as multiplexer control signals for multiplier-free shift-add inference, preserving spike boundaries throughout a four-scale bidirectional feature pyramid. We introduce the Spike-Gated Multi-Scale (SGMS) block, performing receptive field expansion with activity-driven channel selection, implementable with adders and comparators. Evaluated on VisDrone and DOTA and across Nano, Small, and Medium variants, SpikeAD achieves up to 46.2% mAP@50 on VisDrone (+4.8% over SNN prior art), and generalizes to oriented bounding box (77.6% mAP@50 on DOTA) using the proposed SpikeOBB head. Under the Horowitz 45nm arithmetic energy model following standard methodology in SNN literature, SpikeAD achieves up to 18.9x estimated reduction relative to an equivalent MAC-based implementation. We propose the Spike Processing Core (SPC), an RTL compute primitive to validate hardware realizability for reconfigurable and scalable custom accelerator chip design on FPGA/ASIC, highlighting a promising path toward next-generation ultra-low-power neuromorphic processors for aerial object detection. Link to the open-source and open-weight GitHub repository will be added upon publication.

Figures & tables

Fig. 1: Architecture of SpikeAD. The spike encoding stem (CPU/Camera ISP) generates the initial spike tensor. The subsequent inference stage (accelerator-mapped), comprising the backbone, four-scale bidirectional feature pyramid neck, and decoupled head operates strictly via spike-controlled accumulation. The SpikeOBB block adds a dedicated orientation branch for oriented object detection.

Fig. 2: Structure of the Spike MetaFormer Block (shortened as SpikeBlock in the paper), comprising a Spike Spatial Mixer and a Spike Channel Mixer with successive residual connections.

Method	Params (M)	GMACs/GACs	T $\times$ K	Energy (mJ)	$\boldsymbol{\eta}\uparrow$	mAP 50	mAP ${}_{50\text{-}95}$
Two-stage detectors
Faster R-CNN [ 9 ]	41.4	104.0	–	478.4	1 $\times$	39.1	23.6
Cascade R-CNN [ 54 ]	69.3	118.0	–	542.8	1 $\times$	38.5	23.6
Transformer-based detectors
Sparse DETR [ 55 ]	41.0	60.5	–	278.3	1 $\times$	42.5	27.3
Deformable DETR [ 56 ]	40.0	86.5	–	397.9	1 $\times$	42.2	27.1

TABLE I: Comparison on VisDrone-DET-val (640

\times

640, 10 classes). GMACs=GFLOPs/2. Energy computed per Horowitz model [ 53 ] (45 nm, FP32):

E_{\text{MAC}}=4.6

pJ,

E_{\text{AC}}=0.9

pJ.

\eta

= arithmetic energy reduction factor vs. equivalent-MACs ANN. T

\times

K: timesteps

\times

spike levels.

Fig. 3: Integer spike feature maps and spatial firing rates at progressive network stages. Top: representative channel showing discrete spike values $\in\{0,1,2,3,4\}$ . The channel with the most spike activity is selected. Bottom: spatial firing rate, averaged across time and channels. From left to right, we observe progressive abstraction: (a) fine-grained spatial encoding after spike encoding, (b) backbone feature development, (c) highly selective response after the SGMS gating mechanism, and (d) object-focused attention after FPN fusion.

Fig. 4: mAP vs. estimated arithmetic energy (Horowitz 45 nm model) curves: comparison with state-of-the-art methods on the VisDrone benchmark.

Method	Params	GMACs/GACs	Energy(mJ)	PL	BD	BR	GTF	SV	LV	SH	TC	BC	ST	SBF	RA	HA	SP	HC	mAP
Transformer-based oriented detectors
AO2-DETR [ 59 ]	40.8M	152.0	699.2	87.99	79.46	45.74	66.64	78.90	73.90	73.30	90.40	80.55	85.89	55.19	63.62	51.83	70.15	60.04	70.91
ARS-DETR [ 60 ]	41.6M	–	–	86.61	77.26	48.84	66.76	78.38	78.96	87.40	90.61	82.76	82.19	54.02	62.61	72.64	72.80	64.96	73.79
One-stage oriented detectors
Rotated FCOS [ 61 ]	31.9M	103.5	476.1	88.52	77.54	47.06	63.78	80.42	80.50	87.34	90.39	77.83	84.13	55.45	65.84	66.02	72.77	49.17	72.45
S2ANet [ 62 ]	38.5M	99.0	455.4	89.11	82.84	48.37	71.11	78.11	78.39	87.25	90.83	84.90	85.64	60.36	62.60	65.26	69.13	57.94	74.12

TABLE II: Comparison on DOTA-v1.0 test set. All models use single-scale training and testing. Per-class AP and mAP 50 are reported. ⋆ Spike-controlled inference (SPC). The abbreviations refer to Plane (PL), Baseball Diamond (BD), Bridge (BR), Ground Track Field (GTF), Small Vehicle (SV), Large Vehicle (LV), Ship (SH), Tennis Court (TC), Basketball Court (BC), Storage Tank (ST), Soccer-ball Field (SBF), Roundabout (RA), Harbor (HA), Swimming Pool (SP), and Helicopter (HC).

Fig. 5: Sample prediction results on VisDrone and DOTA datasets and comparison with state-of-the-art SNN detector (SpikeYOLO). Left: VisDrone (HBB). Right: DOTA (OBB). SpikeYOLO does not support OBB and we kept the model by using our SpikeOBB detection head to train SpikeYOLO on DOTA for comparison.

Fig. 6: Ablation and explainability visualization via SNN firing heatmaps: evolution of spatial attention across architecture ablations. Global firing rate from left to right: 11.4%, 9.7%, 10.2%, 11.1%, 10.5%.

Small
Variant	Params	GACs	$\boldsymbol{\rho}$	Energy	$\boldsymbol{\eta}\uparrow$	mAP 50	mAP ${}_{50\text{-}95}$
	(M)	(G)	(%)	(mJ)
Baseline	13.2	9.3	27.2	8.8	17.8 $\times$	36.2	20.8
$+$ HRFPN	14.5	12.4	28.5	12.0	16.8 $\times$	38.8	22.9
$+$ MS	13.5	12.5	29.2	12.0	16.4 $\times$	39.0	23.0
$+$ SGMS ⋆	13.5	11.9	27.8	11.4	17.3 $\times$	39.3	23.2

TABLE III: Progressive ablation on VisDrone. GACs are normalized with

\rho

. Baseline: 3-scale FPN with standard SSM and SFC.

+

HRFPN: high-resolution 4-scale bidirectional FPN.

+

MS: SGMS multi-scale dilated mixer without binary gate.

+

SGMS: complete SpikeAD, ⋆ spike-controlled.

\rho

: active spike rate;

Fig. 7: Spike Processing Core (SPC) microarchitecture and datapath with 3-stage pipeline. The spike value acts as a 3-bit control signal selecting a shifted weight into the accumulator via combinatorial logic. Zero spikes disable the datapath via clock-enable gating. The W-SRAM output register is shown for pipeline clarity but lies outside the synthesized SPC boundary. No multiplier circuit is required.

Fig. 8: Illustrative custom chip design mapping: (a) Conceptual architecture of the Sparse Spike-Controlled Accelerator (SSCA) with an optional nonzero-event extractor and FIFO routing spikes to the SPC array, analogous to GPU scheduling but optimized for spike events; only the individual SPC primitive is implemented in RTL in this work; (b) Execution dataflow example for a $\operatorname{SC}_{DW,3}$ on a $5\times 5$ feature map. Only five nonzero input events are dispatched, whereas a dense formulation evaluates all 25 input positions. Actual cycle counts depend on array parallelism, memory organization, fan-out, and scheduling.

Variant	Format	mAP 50	mAP ${}_{50\text{-}95}$	Energy (mJ)
SpikeAD-N	FP32	39.3	23.2	11.4
SpikeAD-N	W8A3	39.1	23.0	1.27
SpikeAD-S	FP32	42.5	25.2	19.3
SpikeAD-S	W8A3	42.3	25.1	2.14
SpikeAD-M	FP32	46.2	27.9	34.8
SpikeAD-M	W8A3	46.0	27.8	3.87

TABLE IV: VisDrone performance under FP32 vs. W8A3 quantization. W8A3 energy relies on INT32 accumulation (0.1 pJ/add).

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Department of Electrical and Photonics Engineering, Technical University of Denmark, Anker Engelunds Vej 1, 2800 Kongens Lyngby, Denmark · Faculty of Engineering, University of Ruhuna, Hapugala,Galle 80000, Sri Lanka · Autonomous Systems Lab, ETH zürich, Leonhardstrasse 21, 8092 Zürich, Switzerland

Edge Inference Spiking Neural Networks Neuromorphic Computing Event-Based Object Detection Real-Time Object Detection

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Real-time object detection on energy-constrained platforms is critical for applications such as UAV-based inspection, autonomous navigation, and mobile robotics. Spiking neural networks (SNNs) on neuromorphic hardware are believed to be significantly more energy-efficient than conventional artificial neural networks (ANNs). In this work, we present a comprehensive methodology for designing general SNN detection architectures targeting neuromorphic platforms, along with the engineering adaptations required to deploy them on the state-of-the-art Neuromorphic processor, Intel Loihi 2. We benchmark SNN-based object detection on Loihi 2 using both frame-based and event-based datasets, comparing performance with ANN-based detection on the NVIDIA Jetson Orin Nano, NVIDIA Jetson Nano B01, and the Apple M2 CPU. Our results show that SNNs on Loihi 2 can perform real-time detection while achieving the lowest per-inference dynamic energy among all platforms. Also, Loihi 2 outperforms the other platforms in terms of power consumption, though ANNs on Jetson Orin Nano achieve higher inference rates. Furthermore, our ANN-to-SNN distillation-aware training enables SNNs to recover 87-100% of the detection accuracy of their ANN counterparts while maintaining lower inference latency; without distillation, SNNs exhibit an 11-27% accuracy drop. These results highlight the potential of neuromorphic systems for energy-efficient, real-time object detection at the edge.

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