Jun 13, 2026, eess.SPJ/K move · Enter open · S save
Anh Tran, Khanh Tran, Cuong Do
School of Engineering and Applied Science, University of Pennsylvania, Philadelphia, PA 19104, USA · VinUni–Illinois Smart Health Center, VinUniversity, Hanoi 100000, Vietnam · College of Engineering and Computer Science, VinUniversity, Hanoi 100000, Vietnam
Continuous cardiac monitoring in wearable devices demands classifiers that are simultaneously accurate, energy-efficient, and deployable on resource-constrained hardware. While deep neural network approaches have demonstrated high classification accuracy for electrocardiogram (ECG) arrhythmia detection, their substantial parameter counts and reliance on multiply-accumulate-intensive operations make them impractical for low-cost edge platforms. In this work, we propose ECG-LDC, a hardware-software co-design framework that adapts Low-Dimensional Computing (LDC) for real-time ECG arrhythmia classification. ECG-LDC employs a dual-encoder architecture with dedicated value and feature codebooks to independently encode morphological waveform features and RR-interval temporal features, enabling effective capture of both intra-beat and inter-beat cardiac dynamics. The framework encompasses data preprocessing, model training, and a hardware accelerator architecture prototyped on the Pynq-Z2 platform. Implemented using binary representations and XOR/XNOR-based operations, ECG-LDC achieves
97.18% accuracy with a memory footprint of only
3.86 kB. ECG-LDC sacrifices approximately
1.8% accuracy versus SOTA TinyML classifiers but achieves
11~
570× reduction in memory usage; among FPGA-based five-class arrhythmia classifiers, it delivers the highest accuracy with up to
2.4× fewer LUTs and zero DSP block utilization, affirming its suitability for real-time arrhythmia detection on resource-constrained wearable platforms.