Optimizing Register Transfer Level (RTL) code is a critical step in Electronic Design Automation (EDA) for improving power, performance, and area (PPA). We present CODMAS (Collaborative Optimization via a Dialectic Multi-Agent System), a framework that combines structured dialectic reasoning with domain-aware code generation and deterministic evaluation to automate RTL optimization. At the core of CODMAS are two dialectic agents: the Articulator, inspired by rubber-duck debugging, which articulates stepwise transformation plans and exposes latent assumptions; and the Hypothesis Partner, which predicts outcomes and reconciles deviations between expected and actual behavior to guide targeted refinements. These agents direct a Domain-Specific Coding Agent (DCA) to generate architecture-aware Verilog edits and a Code Evaluation Agent (CEA) to verify syntax, functionality, and PPA metrics. We introduce RTLOPT, a benchmark of 120 Verilog triples (unoptimized, optimized, testbench) for pipelining and clock-gating transformations. Across proprietary and open LLMs, CODMAS achieves ~25% reduction in critical path delay for pipelining and ~22% power reduction for clock gating, while reducing functional and compilation failures compared to strong prompting and agentic baselines. These results demonstrate that structured multi-agent reasoning can significantly enhance automated RTL optimization and scale to more complex designs and broader optimization tasks.
Figures & tables
Figure 1: Overview of the CodMas framework, illustrating dialectic interaction between agents and iterative refinement of RTL code.
RTLOpt Dataset Statistics
# Pipelining Code Triples
70
# Clock Gating Code Triples
50
Power Range (nW)
∼1−∼19,000
Area Range (μm2)
∼1−∼18,000
Delay Range (ns)
∼15−∼1,600
Table 1: Summary of the RTLOpt Dataset for evaluating pipelining and clock gating optimizations.
Figure 2: Illustration of the complete CodMas architecture, showing dialectic agents (Articulator & Hypothesis Partner), the executor agents (Domain-Specific Coding Agent & Code Evaluation Agent), and the iterative RTL refinement loop (e.g., pipelined array multiplier). The example highlights a pipelined array multiplier optimization, with feedback from different components guiding successive refinements toward improved PPA metrics.
Pipelining
Models
Zero-Shot
Prompting/Agentic
LLM-VeriPPA
CodMas
A ( ↓ )
T ( ↑ )
FR ( ↓ )
A ( ↓ )
T ( ↑ )
FR ( ↓ )
A ( ↓ )
T ( ↑ )
FR ( ↓ )
A ( ↓ )
T ( ↑ )
FR ( ↓ )
GPT-4o
0.985
11.4
54.2
0.982
15.2
49.6
0.986
15.4
39.7
0.960
25.5
19.5
GPT-3.5-turbo
0.989
10.0
58.0
0.988
14.0
51.2
1.008
13.6
43.3
0.972
21.3
23.4
DeepSeek-v2.5
1.009
9.8
57.8
0.986
12.8
50.0
1.025
13.0
42.8
0.979
21.4
22.8
Llama-3
1.045
8.7
61.4
1.181
11.6
53.8
1.116
11.3
47.1
1.032
19.8
25.5
Table 2: Performance comparison on pipelining and clock gating (CG). Pipelining reports Area (A), Timing (T), and Failure Rate (FR); clock gating reports A, Power (P), and FR. Bold indicates best; ↑ higher is better, ↓ lower is better. All improvements are statistically significant ( p<0.01 ) via paired t-tests with standard deviation in Table 6 .
Full
w/o CEA
w/o DA
w/o DKI
Pipelining
T (GPT-4o)
25.5
17.2
12.9
11.5
FR (GPT-4o)
19.5
31.0
38.5
32.3
T (Llama-3)
19.8
12.6
10.4
9.3
FR (Llama-3)
25.5
36.9
44.7
35.8
Clock Gating
Table 3: Component-wise ablation study of CodMas . DA: Dialectic Agents; DKI: Domain Knowledge Injection; CEA: Code Evaluation Agent.
Figure 3: Ablation comparing CODMAS with a shared-memory multi-agent (SMA) variant where the Articulator and Hypothesis Partner roles are combined.
Figure 4: Impact of iterative refinement in CodMas on pipelining timing improvement (%) for easy (left) and hard (right) RTLOpt problems. Early iterations yield substantial gains; later iterations show diminishing or unstable returns, especially for harder cases.
Appendix figures & tables3 assets
Supplementary material from the paper’s appendix.
Appendix
Dataset
Size
Functionality
Synthesizability
Metric-specific
VerilogEval Liu et al. (2023)
156
✓
✗
✗
RTLLM Lu et al. (2024)
30
✓
✓
✗
RTLRewriter Yao et al. (2024)
95
✗
✓
✗
TuRTLe Garcia-Gasulla et al. (2025)
223
✓
✓
✗
CVDP Pinckney et al. (2025)
783
✓
✓
✗
ResBench Guo and Zhao (2025)
56
✓
✓
✗
Appendix
Table 4: Comparison of RTLOpt with prior Verilog datasets. “Metric-specific” indicates whether metric-specific optimization exists or not for evaluation.
Module
Original RTL
CodMas Optimized RTL
Multiplier
Sequential multiply w/o pipeline
Partial product pipelined with inter-stage registers
Adder
Ripple-carry 32-bit adder
Pipelined adder with reduced critical path
Control Logic
Unconditioned enable signals
Handshake-aware control signals with proper gating
Table 5: Example of pipelining transformation and error mitigation under CodMas . Dialectic agents guide structured edits, and the CEA validates correctness and PPA improvements.
CodMas Performance: Mean ± Std over 5 runs
Model
Pipelining
Clock Gating
A ( ↓ )
T ( ↑ )
FR ( ↓ )
A ( ↓ )
P ( ↑ )
FR ( ↓ )
GPT-4o
0.960 ± 0.007
25.5 ± 1.2
19.5 ± 2.1
0.999 ± 0.006
21.7 ± 1.5
21.8 ± 2.3
GPT-3.5-turbo
0.972 ± 0.009
21.3 ± 1.1
23.4 ± 2.4
1.020 ± 0.007
18.8 ± 1.2
24.2 ± 2.0
DeepSeek-v2.5
0.979 ± 0.010
21.4 ± 1.0
22.8 ± 2.3
1.015 ± 0.008
19.0 ± 1.3
23.6 ± 2.1
Llama-3
1.032 ± 0.012
19.8 ± 1.3
25.5 ± 2.5
1.048 ± 0.010
16.5 ± 1.1
26.3 ± 2.4
Appendix
Table 6: Extracted CodMas results with mean and standard deviation over five runs. Metrics: area (A), timing (T), power (P), and failure rate (FR). FR denotes fraction of runs failing syntax, functional, or PPA checks.
Recent advances in large language models (LLMs) have sparked growing interest in automatic RTL optimization for better performance, power, and area (PPA). However, existing methods are still far from realistic RTL optimization. Their evaluation settings are often unrealistic: they are tested on manually degraded, small-scale RTL designs and rely on weak open-source tools. Their optimization methods are also limited, relying on coarse design-level feedback and simple pre-defined rewriting rules. To address these limitations, we present Dr. RTL, an agentic framework for RTL timing optimization in a realistic evaluation environment, with continual self-improvement through reusable optimization skills. We establish a realistic evaluation setting with more challenging RTL designs and an industrial EDA workflow. Within this setting, Dr. RTL performs closed-loop optimization through a multi-agent framework for critical-path analysis, parallel RTL rewriting, and tool-based evaluation. We further introduce group-relative skill learning, which compares parallel RTL rewrites and distills the optimization experience into an interpretable skill library. Currently, this library contains 47 pattern--strategy entries for cross-design reuse to improve PPA and accelerate convergence, and it can continue evolving over time. Evaluated on 20 real-world RTL designs, Dr. RTL achieves average WNS/TNS improvements of 21%/17% with a 6% area reduction over the industry-leading commercial synthesis tool.
Wenji Fang, Yao Lu, Shang Liu +5
Hong Kong University of Science and Technology (HKUST)
LLMs have recently demonstrated strong capabilities in automatic RTL code generation, achieving high syntactic and functional correctness. However, most methods focus on functional correctness while overlooking critical physical design objectives, including Power, Performance, and Area. In this work, we propose a PPA-aware, tool-integrated multi-agent framework for high-quality verilog code generation. Our framework explicitly incorporates EDA tools into a closed-loop workflow composed of a Programmer Agent, a Correctness Agent, and a PPA Agent, enabling joint optimization of functional correctness and physical metrics. To support continuous improvement without model retraining, we introduce an Evolved Memory Mechanism that externalizes optimization experience into structured memory nodes. A dedicated memory manager dynamically maintains the memory pool and allows the system to refine strategies based on historical execution trajectories. Extensive experiments demonstrate that our approach achieves strong functional correctness while delivering significant improvements in PPA metrics. By integrating tool-driven feedback with structured and evolvable memory, our framework transforms RTL generation from one-shot reasoning into a continual, feedback-driven optimization process, providing a scalable pathway for deploying LLMs in real-world hardware design flows.
Yaoxiang Wang, Qi Shi, ShangZhan Li +6
Xiamen University · Tsinghua University · Harbin Institute of Technology
Large Language Models (LLMs) show promise for generating Register-Transfer Level (RTL) code from natural language specifications, but single-shot generation achieves only 60-65% functional correctness on standard benchmarks. Multi-agent approaches such as MAGE reach 95.9% on VerilogEval yet remain untested on harder industrial benchmarks such as NVIDIA's CVDP, lack synthesis awareness, and incur high API costs. We present ChipCraftBrain, a framework combining symbolic-neural reasoning with adaptive multi-agent orchestration for automated RTL generation. Four innovations drive the system: (1) adaptive orchestration over six specialized agents via a PPO policy over a 168-dim state (an alternative world-model MPC planner is also evaluated); (2) a hybrid symbolic-neural architecture that solves K-map and truth-table problems algorithmically while specialized agents handle waveform timing and general RTL; (3) knowledge-augmented generation from a 321-pattern base plus 971 open-source reference implementations with focus-aware retrieval; and (4) hierarchical specification decomposition into dependency-ordered sub-modules with interface synchronization. On VerilogEval-Human, ChipCraftBrain achieves 97.2% mean pass@1 (range 96.15-98.72% across 7 runs, best 154/156), on par with ChipAgents (97.4%, self-reported) and ahead of MAGE (95.9%). On a 302-problem non-agentic subset of CVDP spanning five task categories, we reach 94.7% mean pass@1 (286/302, averaged over 3 runs), a 36-60 percentage-point lift per category over the published single-shot baseline; we additionally lead three of four categories shared with NVIDIA's ACE-RTL despite using roughly 30x fewer per-problem attempts. A RISC-V SoC case study demonstrates hierarchical decomposition generating 8/8 lint-passing modules (689 LOC) validated on FPGA, where monolithic generation fails entirely.