CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization
Organizations: National Taiwan University · IBM Research
Abstract
Optimizing Register Transfer Level (RTL) code is a critical step in Electronic Design Automation (EDA) for improving power, performance, and area (PPA). We present CODMAS (Collaborative Optimization via a Dialectic Multi-Agent System), a framework that combines structured dialectic reasoning with domain-aware code generation and deterministic evaluation to automate RTL optimization. At the core of CODMAS are two dialectic agents: the Articulator, inspired by rubber-duck debugging, which articulates stepwise transformation plans and exposes latent assumptions; and the Hypothesis Partner, which predicts outcomes and reconciles deviations between expected and actual behavior to guide targeted refinements. These agents direct a Domain-Specific Coding Agent (DCA) to generate architecture-aware Verilog edits and a Code Evaluation Agent (CEA) to verify syntax, functionality, and PPA metrics. We introduce RTLOPT, a benchmark of 120 Verilog triples (unoptimized, optimized, testbench) for pipelining and clock-gating transformations. Across proprietary and open LLMs, CODMAS achieves ~25% reduction in critical path delay for pipelining and ~22% power reduction for clock gating, while reducing functional and compilation failures compared to strong prompting and agentic baselines. These results demonstrate that structured multi-agent reasoning can significantly enhance automated RTL optimization and scale to more complex designs and broader optimization tasks.
Figures & tables
| RTLOpt Dataset Statistics | |
|---|---|
| # Pipelining Code Triples | 70 |
| # Clock Gating Code Triples | 50 |
| Power Range | |
| Area Range | |
| Delay Range | |
| Pipelining | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Models | Zero-Shot | Prompting/Agentic | LLM-VeriPPA | CodMas | ||||||||
| A ( ) | T ( ) | FR ( ) | A ( ) | T ( ) | FR ( ) | A ( ) | T ( ) | FR ( ) | A ( ) | T ( ) | FR ( ) | |
| GPT-4o | 0.985 | 11.4 | 54.2 | 0.982 | 15.2 | 49.6 | 0.986 | 15.4 | 39.7 | 0.960 | 25.5 | 19.5 |
| GPT-3.5-turbo | 0.989 | 10.0 | 58.0 | 0.988 | 14.0 | 51.2 | 1.008 | 13.6 | 43.3 | 0.972 | 21.3 | 23.4 |
| DeepSeek-v2.5 | 1.009 | 9.8 | 57.8 | 0.986 | 12.8 | 50.0 | 1.025 | 13.0 | 42.8 | 0.979 | 21.4 | 22.8 |
| Llama-3 | 1.045 | 8.7 | 61.4 | 1.181 | 11.6 | 53.8 | 1.116 | 11.3 | 47.1 | 1.032 | 19.8 | 25.5 |
| Full | w/o CEA | w/o DA | w/o DKI | |
|---|---|---|---|---|
| Pipelining | ||||
| T (GPT-4o) | 25.5 | 17.2 | 12.9 | 11.5 |
| FR (GPT-4o) | 19.5 | 31.0 | 38.5 | 32.3 |
| T (Llama-3) | 19.8 | 12.6 | 10.4 | 9.3 |
| FR (Llama-3) | 25.5 | 36.9 | 44.7 | 35.8 |
| Clock Gating | ||||
Appendix figures & tables3 assets
Supplementary material from the paper’s appendix.
Appendix
| Dataset | Size | Functionality | Synthesizability | Metric-specific |
|---|---|---|---|---|
| VerilogEval Liu et al. (2023) | 156 | ✓ | ✗ | ✗ |
| RTLLM Lu et al. (2024) | 30 | ✓ | ✓ | ✗ |
| RTLRewriter Yao et al. (2024) | 95 | ✗ | ✓ | ✗ |
| TuRTLe Garcia-Gasulla et al. (2025) | 223 | ✓ | ✓ | ✗ |
| CVDP Pinckney et al. (2025) | 783 | ✓ | ✓ | ✗ |
| ResBench Guo and Zhao (2025) | 56 | ✓ | ✓ | ✗ |
| Module | Original RTL | CodMas Optimized RTL |
|---|---|---|
| Multiplier | Sequential multiply w/o pipeline | Partial product pipelined with inter-stage registers |
| Adder | Ripple-carry 32-bit adder | Pipelined adder with reduced critical path |
| Control Logic | Unconditioned enable signals | Handshake-aware control signals with proper gating |
| Observed Errors in Baselines | Syntax errors, functional mismatches, unmet PPA targets | |
| Corrected by CodMas | All syntax errors fixed, functional simulation passes, critical path reduced | |
| CodMas Performance: Mean Std over 5 runs | ||||||
|---|---|---|---|---|---|---|
| Model | Pipelining | Clock Gating | ||||
| A ( ) | T ( ) | FR ( ) | A ( ) | P ( ) | FR ( ) | |
| GPT-4o | 0.960 0.007 | 25.5 1.2 | 19.5 2.1 | 0.999 0.006 | 21.7 1.5 | 21.8 2.3 |
| GPT-3.5-turbo | 0.972 0.009 | 21.3 1.1 | 23.4 2.4 | 1.020 0.007 | 18.8 1.2 | 24.2 2.0 |
| DeepSeek-v2.5 | 0.979 0.010 | 21.4 1.0 | 22.8 2.3 | 1.015 0.008 | 19.0 1.3 | 23.6 2.1 |
| Llama-3 | 1.032 0.012 | 19.8 1.3 | 25.5 2.5 | 1.048 0.010 | 16.5 1.1 | 26.3 2.4 |
Electronic Design Automation
Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.
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