Can an Actor-Critic Optimization Framework Improve Analog Design?

Sounak Dutta; Fin Amin; Sushil Panda; Jonathan Rabe; Yuejiang Wen; Paul Franzon

cs.LGMar 25, 2026

Can an Actor-Critic Optimization Framework Improve Analog Design?

Authors: Sounak Dutta, Fin Amin, Sushil Panda, Jonathan Rabe, Yuejiang Wen, Paul Franzon

Organizations: North Carolina State University, Department of Electrical and Computer Engineering, Raleigh, North Carolina, USA

Abstract

Analog design often slows down because even small changes to device sizes or biases require expensive simulation cycles, and high-quality solutions typically occupy only a narrow part of a very large search space. While existing optimizers reduce some of this burden, they largely operate without the kind of judgment designers use when deciding where to search next. This paper presents an actor-critic optimization framework (ACOF) for analog sizing that brings that form of guidance into the loop. Rather than treating optimization as a purely black-box search problem, ACOF separates the roles of proposal and evaluation: an actor suggests promising regions of the design space, while a critic reviews those choices, enforces design legality, and redirects the search when progress is hampered. This structure preserves compatibility with standard simulator-based flows while making the search process more deliberate, stable, and interpretable. Across our test circuits, ACOF improves the top-10 figure of merit by an average of 38.9% over the strongest competing baseline and reduces regret by an average of 24.7%, with peak gains of 70.5% in FoM and 42.2% lower regret on individual circuits. By combining iterative reasoning with simulation-driven search, the framework offers a more transparent path toward automated analog sizing across challenging design spaces.

Figures & tables

Figure 1. Example of interactions between our actor and critic during analog sizing optimization. Our framework defines a closed-loop optimization process that alternates between proposal, audit, search, and reflection.

Figure 2. An overview of our actor–critic optimization framework (ACOF). At each time step,

n

, the actor proposes a candidate search region

\tilde{\Omega}_{n}

, the critic adjusts it to a PDK-legal region

\Omega_{n}^{+}

, BO selects candidates

x\in\Omega_{n}^{+}

for simulation, and simulator outcomes are summarized into

e_{n}

for the next round. ACOF is agnostic to the specific choice of BO.

		Top-10 Design Quality					Reliability (%)		Exploration/Exploitation
	Method	Gain (dB) $\uparrow$	UGBW (MHz) $\uparrow$	PM (deg) $\uparrow$	Power (mW) $\downarrow$	FoM $\uparrow$	Sim. Valid $\uparrow$	Phys. Feasible $\uparrow$	Regions $\uparrow$	Regret $\downarrow$
130nm 12 Params	Target Spec.	85.00	900.00	100.00	0.554	0.00	-	-	-	-
[0.4pt/1.2pt]	ACOF	83.65 0.64	785.30 39.71	101.35 1.13	0.658 0.045	-0.19 0.01	97.0 0.1	86.2 1.4	2.0 0.0	0.25 0.01
	LEDRO	83.15 0.55	717.63 45.51	111.89 0.74	0.657 0.029	-0.24 0.02	95.4 0.9	78.9 1.8	2.7 0.3	0.30 0.01
	Pure-BO	76.24 1.45	673.92 22.65	128.23 3.27	0.587 0.014	-0.39 0.02	81.0 0.3	26.9 0.1	3.0 0.8	0.37 0.02
	Human Expert	72.77	851.48	173.59	0.821	-0.45	-	-	-	-

Table 1. Results across the four test circuits. Each circuit forms one multi-row block at left. Values are mean with standard errors in subscripts. Bold indicates the best baseline method within each circuit and metric. Qwen was used as the LLM.

Figure 3. UMAP projections of the sizing parameters illustrate how the design space was explored over optimization rounds. To aid visualization, we outlined regions being explored in the current rounds in red and rendered the cumulative explored designs from past rounds in gray. ACOF judiciously explores the design space by targeting regions corresponding to high performance–as indicated by the higher round-wise Avg and Max FoM. Our technique successfully explored the regions above $\texttt{UMAP Component 2}>1$ . On the other hand, the baselines were apprehensive of exploration and achieved worse FoMs.

Panel of Figure 4 — Figure 4. The circuit schematics of our benchmarks. For an OpAmp, gain, bandwidth, phase margin, and power are coupled design specifications. Higher DC gain can introduce additional poles; this affects phase margin. Also, improving UGBW usually requires higher bias current and therefore higher power. The design must therefore balance gain, UGBW, power, and phase margin.

Panel of Figure 5 — Figure 5. Exponentially-smoothed FoM trajectories for the 180nm 21-parameter folded-cascode benchmark using variants of GPT as the LLM. Subcaptions report the across-run mean of the per-run top-10 mean FoM. Optimization steps for the LLM-based methods begin at 200 because both are initialized with $\mathcal{C}_{0}=200$ seed designs generated by Pure-BO. After initialization, the LLM-based methods update the optimization ranges every 100 steps.

Model	Method	Top-10 FoM $\uparrow$	Phys. Feasible (%) $\uparrow$	Regret $\downarrow$
GPT-4o Mini	ACOF	-0.359 0.018	67.1 3.5	0.395 0.019
GPT-4o Mini	LEDRO	-0.643 0.015	37.8 2.3	0.579 0.021
GPT-5	ACOF	-0.271 0.024	99.4 0.0	0.313 0.019
GPT-5	LEDRO	-0.319 0.035	80.9 8.9	0.381 0.024

Table 2. Results on the 180nm 21-parameter folded-cascode benchmark using variants of GPT as the LLM.

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Sep 22, 2026J/K move · Enter open · S save

AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing

Yijia Hao, Pratibha Verma, Dongxu Guo, Cristian Sestito+3

Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, UK · Department of Electrical Engineering, Indian Institute of Technology Indore, India · School of Informatics, The University of Edinburgh, UK+1

Large Language Model-Guided Optimization Electronic Design Automation Analog Circuit Sizing Multi-Agent LLMs LLM Agent Planning

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Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled technologies. Although recent large language model (LLM)-based methods show promise in improving sample efficiency and interpretability, existing approaches often lack explicit circuit-topology understanding and are mainly evaluated on relatively simple analog building blocks. This paper presents a multi-agent LLM-based framework for complex analog circuit sizing. The proposed framework first analyzes the circuit topology and decomposes the netlist into functional blocks and substructures. It also extracts lightweight design knowledge for reuse. Based on the extracted topology and knowledge, a planner coordinates multiple role-specialized sizing agents to update design variables and achieve global performance specifications. This workflow mimics the collaborative process of an expert analog design team and provides a structured, interpretable, and simulation-driven optimization procedure. The framework was validated on eight circuits, with the largest design containing up to 55 transistors and 60 sizing variables. Notably, for the LDO benchmark, the proposed method achieved a 60% success rate with an average of 83 iterations, where classical optimizers failed to find feasible solutions. Further, ablation studies demonstrate that topology understanding, design-knowledge infusion, and agent specialization provide complementary benefits. The source code is available to support reproducibility.

Abstract

Analog Circuit Sizing

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