Agent-Orchestration in Autonomous Chip Design

Linyang Li

cs.AIAug 14, 2026

Agent-Orchestration in Autonomous Chip Design

Authors: Linyang Li

Organizations: Nova Silicon

Abstract

Recent developments in large language models (LLMs) and tool-using agents encourage people to explore the potential of using agents in chip design. The core question is what kind of AI we really need in such a sophisticated industry. To this end, we bring the idea of modeling a chip-design superintelligence as an enormous AI-organization.

LLM Agent Orchestration

Large language model agent orchestration coordinates models, tools, and workflows to complete complex tasks reliably and efficiently.

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Can Agents Design Better Chips with a Higher Level Abstraction?

Zijian Ding, Yang Zou, Yizhou Sun, Jason Cong

UCLA Los Angeles, CA, USA

Electronic Design Automation LLM Agent Workflow Optimization

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Large Language Model (LLM) agents are increasingly being explored for chip design, but most existing approaches operate directly at RTL. We ask whether agents can design better chips by leveraging higher-level abstractions. We compare Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and combine Agent-based HLS Design with Post-HLS RTL Refinement as Agent-based HLS with RTL Refinement (AHRR). We use FPGAs as a practical, easy-to-deploy platform for end-to-end evaluation, but note that the design-flow tradeoffs we study are largely independent of the target technology. Across a diverse 11-tasks benchmark suite, AHRR achieves a 2.6

\times

geometric-mean speedup over Direct RTL Design across our benchmark suite. Case studies show that HLS distills design knowledge into abstractions that agents can leverage, while RTL refinement recovers lower-level optimization opportunities. Together, these results make AHRR a promising workflow for agentic chip design. The code and evaluation artifacts are available at https://github.com/ZijD/AHRR.

Abstract

LLM Agent Orchestration

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