Gen-TAS: A Generative AI-Aided Hardware-Software Task Allocation Framework for FPGA-GPP Heterogeneous Systems

Mary Kong; Yuqin Zhao; Semih Vazgecen; Cristian Sestito; Themis Prodromakis

cs.ARAug 28, 2026

Gen-TAS: A Generative AI-Aided Hardware-Software Task Allocation Framework for FPGA-GPP Heterogeneous Systems

Authors: Mary Kong, Yuqin Zhao, Semih Vazgecen, Cristian Sestito, Themis Prodromakis

Organizations: Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering, University of Edinburgh, UK

Abstract

FPGA-GPP heterogeneous systems combine software flexibility with the performance and energy efficiency of reconfigurable hardware. However, determining which application tasks should execute on the GPP or FPGA requires extensive expertise and design-space exploration, particularly when user objectives vary across latency, communication, resource utilisation, and power. This paper proposes Gen-TAS, a knowledge-grounded LLM framework for user-specific FPGA-GPP task allocation. By combining task-graph analysis with RAG, Gen-TAS grounds LLM reasoning in historical implementation knowledge and generates multiple explainable strategies tailored to the specified objectives. Human-in-the-loop selection and a deterministic backend connect LLM-generated decisions to reproducible FPGA SoC implementations. Experiments on CNN and SDR workloads across multiple LLMs demonstrate stable, requirement-driven allocation. Under latency-oriented objectives, implementations following the selected strategies achieve speedups of up to 2.45 $\times$ and 92.53 $\times$ , respectively, relative to the corresponding all-GPP baselines while other objectives select strategies that trade some acceleration performance for FPGA-GPP communication, resource utilisation, or FPGA power.

Figures & tables

Method	Platform / Scope	AI / Knowledge	Limitation or differentiator
EcoSys [ 15 ]	FPGA-GPP/ DNN video analytics	None/ profiling and analytical models	Application-specific and profiling-based; limited requirement interpretation
StreamBlocks [ 16 ]	FPGA-GPP/ streaming tasks	None/ execution profiles	Profile-guided task parallelism; restricted to streaming applications
CariPy [ 6 ]	FPGA/ accelerator generation	Generative AI/ knowledge base	Hardware-generation focused; no HW/SW boundary reasoning or heterogeneous deployment
SECDA-DSE [ 8 ]	FPGA/ HLS accelerator DSE	Generative AI/ KB and RAG	Accelerator-template DSE; no general HW/SW task allocation
Gen-TAS (This Work)	FPGA-GPP/ function-level allocation	Agentic AI/ KB and RAG	Requirement-driven; explainable allocation and deterministic implementation

TABLE I: Comparison with FPGA and FPGA-GPP partitioning methods.

Fig. 1: Gen-TAS workflow: (a) design-context construction from user requirements, HLS code, and implementation knowledge; (b) agentic AI with task/dataflow analysis and RAG for FPGA–GPP partition generation and user selection; (c) deterministic Vitis HLS/Vivado implementation of the selected strategy; and (d) PYNQ-based execution and measurement of latency, resources, and power.

Fig. 2: Requirement- and retrieval-driven FPGA-GPP task allocation in Gen-TAS: (a) design-context construction from natural-language requirements, HLS C/C++ code, and retrieved implementation knowledge; and (b) agentic AI combining task/dataflow analysis, RAG, and an LLM to generate, justify, and rank candidate partitions for user selection before deterministic implementation and hardware validation.

Workload	Objective	LLM	Rank-1	Consistency	Latency (ms)	Speedup	Implementation Metrics							LLM Time (s)
Workload	Objective	LLM	Rank-1	Consistency	Latency (ms)	Speedup	LUT	FF	DSP	BRAM	FPGA P. (W)	GPP P. (W)	Total P. (W)	LLM Time (s)
CNNImageProc	Constrained Latency	GPT-5.6 Sol	FFFFG	5/5	$15.494\pm 0.003$	$2.445\pm 0.001\times$	6763 (18.7%)	6189 (10.2%)	8 (68.0%)	42 (27.6%)	0.714 (6.9%)	2.738	3.451	$70.293\pm 5.169$
		Gemini 3.6 Flash	FFFFG	5/5	$15.494\pm 0.003$	$2.445\pm 0.001\times$	6763 (18.7%)	6189 (10.2%)	8 (68.0%)	42 (27.6%)	0.714 (6.9%)	2.738	3.451	$35.994\pm 8.547$
		Claude Fable 5	FFFFG	3/5	$15.494\pm 0.003$	$2.445\pm 0.001\times$	6763 (18.7%)	6189 (10.2%)	8 (68.0%)	42 (27.6%)	0.714 (6.9%)	2.738	3.451	$85.202\pm 3.240$
	Communication-Aware	GPT-5.6 Sol	FFFFG	5/5	$15.494\pm 0.003$	$2.445\pm 0.001\times$	6763 (18.7%)	6189 (10.2%)	8 (68.0%)	42 (27.6%)	0.714 (6.9%)	2.738	3.451	$66.908\pm 4.870$
		Gemini 3.6 Flash	FFFFG	4/5	$15.494\pm 0.003$	$2.445\pm 0.001\times$	6763 (18.7%)	6189 (10.2%)	8 (68.0%)	42 (27.6%)	0.714 (6.9%)	2.738	3.451	$30.467\pm 0.947$

TABLE II: Gen-TAS rank-1 partitioning, implementation cost, and hardware-cost reduction across design objectives and LLMs (five runs per configuration).

Fig. 3: LLM comparison for (a) CNNImageProc and (b) CAMC across objective satisfaction, token efficiency, and LLM latency efficiency. Results aggregate five independent runs across four Gen-TAS design objectives for each LLM. Higher values indicate better performance.

Heterogeneous Computing

Heterogeneous computing studies how to coordinate different processors, accelerators, and memory systems to improve performance, efficiency, and cost.

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Can large language models generate not just correct, but fast hardware? This paper investigates the question in financial FPGA design, where 5-10 nanoseconds of latency determines competitive advantage and designs iterate continuously as protocols, strategies, and regulations evolve. FinHardBench, a benchmark of 33 financial computing tasks, is presented together with three experiments that mirror the real-world FPGA iteration cycle: generating new modules from specifications, tuning system-level configurations across a 6-stage trading pipeline, and adapting existing modules to specification changes. Evaluation of six LLMs on 1530+ experiment rounds yields three findings: (1) models achieve 19-61% functional correctness with timing degradation up to 13.7

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Abstract

Heterogeneous Computing

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