Large Language Model (LLM) agents are increasingly being explored for chip design, but most existing approaches operate directly at RTL. We ask whether agents can design better chips by leveraging higher-level abstractions. We compare Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and combine Agent-based HLS Design with Post-HLS RTL Refinement as Agent-based HLS with RTL Refinement (AHRR). We use FPGAs as a practical, easy-to-deploy platform for end-to-end evaluation, but note that the design-flow tradeoffs we study are largely independent of the target technology. Across a diverse 11-tasks benchmark suite, AHRR achieves a 2.6× geometric-mean speedup over Direct RTL Design across our benchmark suite. Case studies show that HLS distills design knowledge into abstractions that agents can leverage, while RTL refinement recovers lower-level optimization opportunities. Together, these results make AHRR a promising workflow for agentic chip design. The code and evaluation artifacts are available at https://github.com/ZijD/AHRR.
Figures & tables
Figure 1. The four design flows studied in this paper. In (i) Direct RTL Design, the agent writes RTL directly from the specification. In (ii) Agent-based HLS Design, the agent writes HLS C++ and Vitis HLS generates RTL. In (iii) Post-HLS RTL Refinement, the agent further refines HLS-generated RTL. In (iv) Post-Compiler HLS Refinement, a domain-specific compiler generates the initial HLS C++, which the agent further refines. Flow Diagram
Task
Category
Interface
Arithmetic
Dynamic axis
Scaled down
LLM1 llm_decode_attention_kv
LLM decode attention over a KV cache ( Grattafiori et al., 2024 )
m_axi
fixed
seq_len
no
LLM2 llm_norm_quant_linear
fused RMSNorm + quantize + INT8 linear ( Zhang et al., 2026a )
m_axi
mixed
seq_len
yes - 12 tokens
GEM1 gemm_i8_512
dense INT8 GEMM, two variants: 3/12 AXI
m_axi
fixed
none
no
MEM1 mem_bm25_gather_score
BM25 retrieval ranking over postings ( Robertson and Zaragoza, 2009 )
ap_memory
fixed
none
no
MEM2 mem_kv_page_compact
paged-KV ( Kwon et al., 2023 ) Prepare Memory stage
ap_memory
fixed
seq_len
no
MEM3 mem_lserve_page_select
LServe-style page selection ( Yang et al., 2025 )
ap_memory
fixed
none
no
Table 1. The 11-task benchmark suite spans LLM inference, agentic memory, robotics, and GEMM. Selected tasks use fixed-point arithmetic to avoid floating-point IP. Dynamic dimensions are preserved when possible, and some workloads are scaled down to reduce RTL simulation time.
Parameter
Value
device
AMD Alveo U55C (xcu55c-fsvh2892-2L-e)
toolchain
Vitis 2025.2, out of context (no shell)
agents
gemini-3.1-pro (high), gpt-5.6-sol (xhigh)
maximum rounds
5
agent round timeout
60 min
evaluation timeout
RTL sim 75 min, syn + PnR 90 min
Table 2. Parameters fixed across experiments.
(i) Direct RTL Design
(ii) Agent-based HLS Design
(ii) → (iii) AHRR
Task
Model
ms
speedup
ms
speedup
ms
speedup
GEM1 (3 AXI)
gemini
2.19
1.00 ×
0.40
5.43 ×
–
–
gpt
1.31
1.00 ×
0.55
2.40 ×
–
–
LLM1
gemini
1.29
1.00 ×
0.43
3.02 ×
0.43
3.02 ×
gpt
2.54
1.00 ×
0.47
5.37 ×
0.43
5.87 ×
LLM2
gemini
×
0.20
–
0.20
–
Table 3. Comparison of the specification-driven design workflows. Speedups are relative to Direct RTL Design on the same task and model. Geometric means include only pairs with a valid Direct RTL baseline; n denotes the number of included pairs. AHRR has n=13 because Post-HLS RTL Refinement was not evaluated on the two GEM1 (3 AXI) cases.
Figure 2. Performance and resource comparison of Agent-based HLS Design and Direct RTL Design. With HLS, state-of-the-art agents achieve a 2.31 × geometric-mean speedup over direct RTL design. Performance and resource comparison of Agent-based HLS Design and Direct RTL Design.
Figure 3. Per-round progress of Post-HLS RTL Refinement, normalized to the HLS-generated RTL that seeds each experiment. All axes are oriented so that higher is better. LUT and DSP savings are shown alongside speedup to capture the tradeoff between area and performance. We also include SHL1/SHL2 to illustrate that Post-HLS RTL Refinement becomes challenging when simulation time is long. post hls rtl optimization
SHL1
SHL2
GEM1
DS-compiler
StreamHLS
StreamHLS
AutoSA
Compiler baseline
1.0
1.0
1.0
Post-Compiler HLS Refinement
1.0 / 1.0
3.3 / 1.7
1.3 / 1.2
Table 4. Post-Compiler HLS Refinement relative to the domain-specific compiler baseline, reported as Gemini / GPT. We use StreamHLS for SHL1/SHL2 and AutoSA for GEM1.
Figure 4. Abstractions distill design knowledge for agents. On the left, the same agent implements ROB1 through HLS and direct RTL Design. The HLS design uses two pragmas to produce 256-way parallelism, while the direct RTL design achieves only 32/8-way parallelism despite requiring more Verilog than HLS C++. On the right, across six tasks, the weaker model nearly matches the stronger model when both operate through HLS. case study 1
Figure 5. Agents recover inefficiencies left by compiler heuristics. The StreamHLS design passes through Post-Compiler HLS Refinement and Post-HLS RTL Refinement. At HLS level, Four whole tensors are rewritten to two rows and a window, reducing cycle count by 61%. At RTL level, a multiplier with a pinned operand becomes a lookup table, reducing the clock period by 9% at unchanged cycle count. case study 2
Figure 6. Agents optimize timing and area beneath the HLS schedule: on MEM3, moving the min/max selection before multiplication cuts DSP usage and cuts LUTs by 2.2 × without changing the cycle count. On ROB1, rewriting the comparison removes a subtractor from the critical path and reduces the clock period from 3.60 to 3.31 ns. case study 3