CorrectRTL: Boost RTL Generation Quality Through Automated Self-Correction with Instruction Decomposition

Jing Wang; Shang Liu; Hangan Zhou; Wenji Fang; Yuchao Wu; Yugao Zhu; Zhiyao Xie

cs.AIOct 18, 2026

CorrectRTL: Boost RTL Generation Quality Through Automated Self-Correction with Instruction Decomposition

Authors: Jing Wang, Shang Liu, Hangan Zhou, Wenji Fang, Yuchao Wu, Yugao Zhu, Zhiyao Xie

Organizations: Hong Kong University of Science and Technology Clear Water Bay, Hong Kong

Abstract

Large language models (LLMs) have shown strong promise in specification-to-RTL generation. Among the explorations, the self-correction paradigm has significantly advanced LLM-based RTL generation. However, two challenges limit further progress. Existing benchmarks are saturated by advanced LLMs, leaving little room to evaluate the agentic self-correction framework. The monolithic self-correction paradigm rewrites the entire design at once, where LLMs are susceptible to error confusion and corruption of originally correct code. To address the benchmark challenge, we contribute ScaleBench, a more challenging benchmark of 200 complex RTL designs. To address the challenge in methodology, we propose CorrectRTL, an agentic framework that realizes a new decompose-then-correct paradigm, in which the LLM agent explicitly decouples scaffold construction from detailed implementation. CorrectRTL contributes three core techniques: (1)Structure-oriented decomposition, (2)Snippet-based RAG, and (3)~SVA-based self-correction. On ScaleBench, CorrectRTL improves Pass@1 from 20.5% to 49.0% (+28.5%). On VerilogEval, CorrectRTL achieves up to 96.1% Pass@1, demonstrating consistent improvements across both simple and complex designs.

Figures & tables

Figure 1. Overview of CorrectRTL. (1) Existing approaches rely on testbenches or reference code for self-correction, which are unreliable or impractical. (2) CorrectRTL combines structure-oriented decomposition, snippet-based RAG, and SVA-based self-correction to improve both generation quality and error identification.

Syntax error correction only
Method	Instr.	SVA-based	Self-corr.	Snippet	Correct
Method	decomp.	ident.	w/o golden TB	RAG	func.
HDLDebugger ( Yao et al., 2024 )
RTLFixer ( Tsai et al., 2024 )
Self-corr. relying on manually written golden testbench
MAGE ( Zhao et al., 2024 )					✓

Table 1. Comparison of related works. TB = testbench. CorrectRTL is the first to combine decomposition, SVA-based identification, and snippet-level RAG for RTL generation.

Symbol	Meaning
$\mathcal{S}$	Design specification (natural language)
$f_{\theta}$	LLM with parameters $\theta$
$\mathcal{C}$ , $\mathcal{C}^{\prime}$	Generated / corrected RTL code
$\mathcal{C}_{i}$ , $\mathcal{C}_{i}^{\prime}$	RTL code block $i$ (generated / corrected)
$\mathcal{I}_{i}^{\text{R}}$ , $\mathcal{I}_{i}^{\text{A}}$	RTL / SVA instruction for block $i$
$\mathcal{A}_{i}$	SVA generated for block $i$

Table 2. Notation used in this paper.

Benchmark	#Designs	Avg LoC	Max LoC	Baseline
VerilogEval ( Liu et al., 2023 )	156	16	64	80.1%
RTLLM ( Lu et al., 2024 )	50	48	175	68.0%
ScaleBench	200	120	348	20.5%

Table 3. Benchmark comparison. ScaleBench provides larger designs that are more challenging for LLMs.

Code snippets (by structural block type)
Block type	Snippets	Target logic
Sequential block	$6{,}092$	registers, counters, FSM state
Assign group	$2{,}218$	control fan-out, datapath
Combinational block	$936$	muxes, decoders, arithmetic
Total	$\mathbf{9{,}246}$
SVA templates (by invariant family)

Table 4. Composition of the curated RAG database. Both sub-datasets share the same spec-snippet embedding key.

Figure 2. Overview of CorrectRTL framework, orchestrating a multi-agent system with four phases. Phase 2 is augmented with snippet-based RAG from a database constructed via the same decomposition as Phase 1.

Figure 3. Two-step workflow of RAG dataset construction.

Figure 4. Hierarchical tree $\mathcal{T}$ for a 16-bit adder.

Base LLM	Method	VerilogEval Human v1	VerilogEval Machine v1	VerilogEval Human v2	RTLLM v1.1	RTLLM v2	ScaleBench
		(156 designs)	(143 designs)	(156 designs)	(50 designs)	(50 designs)	(200 designs)
GPT-4o ( Achiam et al., 2023 )	Direct generation	59.0%	69.2%	68.6%	69.1%	67.2%	0 9.5%
	RTLFixer ( Tsai et al., 2024 )	61.5%	73.4%	69.2%	69.1%	67.8%	10.5%
	VeriAssist ( Huang et al., 2024 )	65.3%	74.8%	70.5%	71.2%	67.1%	12.0%
	AutoVeriFix ( Tan et al., 2025 )	76.4%	83.3%	79.8%	74.3%	69.3%	14.5%
	CorrectRTL	85.2% (+26.2)	87.1% (+17.9)	85.3% (+16.7)	77.4% (+8.3)	73.2% (+6.0)	22.0% (+12.5)

Table 5. Overall functional correctness (Pass@1) across backbones and self-correction methods.

Decomposition configuration	Step 1	Step 2	Identification (Step 3)		Correction (Step 3)		Final Pass@1
Decomposition configuration	Gen Pass@1	+RAG Pass@1	Recall	FN	Fix	Regression	Pass@1
Vanilla RTL generation	20.5%	—	—	—	0.0%	0.0%	20.5%
Code-level decomposition	20.5%	20.5%	42%	10%	3.5%	0.3%	23.7%
Vanilla spec decomposition	20.5%	28.0%	50%	8%	5.2%	0.4%	32.8%
CorrectRTL (Structure-oriented decomposition)	28.0%	40.0%	68%	5%	9.2%	0.2%	49.0%

Table 6. Ablation of the four decomposition configurations on ScaleBench (200 designs, Claude Sonnet 4.5).

Variant	Compile	Correct	Precision	Recall
	on Step 2	on Golden		on fail
Vanilla RTL Gen	—	—	—	—
Code-level Decomp	55%	52%	63%	42%
Vanilla spec Decomp	78%	70%	74%	50%
CorrectRTL	92%	85%	88%	68%

Table 7. Ablation study on SVA quality on ScaleBench.

Figure 5. Pass@1, structural similarity (SSim), and SER by ScaleBench LoC bucket for the four ablation configurations based on the Sonnet 4.5.

Figure 6. Pass@1 (left) and SER (right) versus design complexity (LoC bucket) on ScaleBench for Claude Sonnet 4.5.

RTL Code Generation

Register-transfer-level (RTL) code generation turns hardware specifications into synthesizable circuits, balancing functional correctness with area, timing, and power.

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Jun 4, 2026J/K move · Enter open · S save

CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

Mohammad Akyash, Nowfel Mashnoor, Kimia Azar, Hadi Kamali

Department of Electrical and Computer Engineering (ECE), University of Central Florida, Orlando, FL 32816, USA

Code Generation LLM-Based Program Synthesis RTL Code Generation Causal Interventions in Language Models LLM Code Generation

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Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design. Unlike typical natural language (and software coding) tasks, LLM-based RTL code generation demands strict cycle accuracy with concurrency, where minor logical errors can render a circuit unusable or insecure. While prior work has explored hallucination mitigation via external verification, self-evaluation prompts, retrieval-augmented prompting, domain specific fine-tuning, agentic solutions, and reasoning, these approaches largely overlook the attention-oriented internal mechanisms of LLMs that may inherently correlate with RTL correctness. This work proposes CASS-RTL, a first-of-its-kind framework for discovering and leveraging LLMs' correctness-aware components to guide RTL generation toward functionally accurate outputs. We (i) identify attention heads whose activation patterns consistently differentiate correct from incorrect RTL; (ii) construct a low-dimensional subspace capturing correctness-relevant signals; and (iii) design a lightweight, geometry-aware intervention that steers the model at inference time. CASS-RTL is fully model-agnostic, requires no additional supervision or retraining, and readily integrates into existing models. Empirically, we evaluate CASS-RTL on multiple models and observe 10%-20% improvement in pass@1/5/10 accuracy on VerilogEval and 5% improvement on CVDP, demonstrating the effectiveness of our method in enhancing reliability without sacrificing model efficiency or requiring a large labeled dataset for fine-tuning.

Abstract

RTL Code Generation

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