Toward Agentic AI for the 6G Physical Layer: From Algorithm Discovery to Verified Baseband Silicon

Eric Mittag; Lukas Brechtel; Maximilian Stark; Hans D. Schotten

cs.AIOct 20, 2026

Toward Agentic AI for the 6G Physical Layer: From Algorithm Discovery to Verified Baseband Silicon

Authors: Eric Mittag, Lukas Brechtel, Maximilian Stark, Hans D. Schotten

Organizations: German Research Center for Artificial Intelligence (DFKI), Kaiserslautern, Germany · CTO System Innovation, NXP Semiconductors, Hamburg, Germany · RPTU University Kaiserslautern-Landau, Germany

Abstract

6G will be designed faster than it can be built: AI-driven search already proposes physical-layer algorithms at machine speed, while carrying a single one onto embedded baseband silicon remains specialist work. That silicon imposes hard memory and numeric limits, but also exposes cost structures a GPU lacks, and a design flow that never runs on the target sees neither. We present an agentic workflow in which an LLM coding agent implements algorithms on a commercial baseband SoC, optimizes them down to agent-written vector assembly, and validates them on silicon. The agent is guided by a knowledge base of measured platform facts, checked at every step against evaluators it is instructed never to edit, and metered per phase. We showcase the workflow on an AI-discovered orthogonal time frequency space (OTFS) detector portfolio on the open 6G4All platform. It yields twelve kernels that run cycle-exactly on silicon, their optimized versions at 18k-405k cycles (30-660 $μ$ s) per frame. It also yields a new detector shaped by the chip's measured costs that needs 13.9% fewer cycles than the port of the discovered detector while matching its error rate, with a measured edge our evaluation cannot statistically resolve, a structure that a hardware-blind search objective had no reason to find. What is not specific to OTFS is the workflow: an LLM agent exploring an implementation space under real hardware limits, with the cost of every choice measured rather than assumed.

Figures & tables

Grid	top_k	Coefficients	Footprint
$64\times 64$ (selected soln.)	2560	$1.05\cdot 10^{7}$	62.9 MB
$64\times 64$ (alt. Pareto pt.)	1536	$6.29\cdot 10^{6}$	37.7 MB
$8\times 4$ (top-8 view)	8	$2.56\cdot 10^{2}$	1.5 kB
Available on target (DMEM usable $+$ IPPU)			27.9 kB
of which portable to the cycle simulator			20.4 kB

TABLE I: Design rule check of the published channel representation against the target: footprint of the sparse delay-Doppler view at 16-bit I/Q plus 16-bit index; top_k is the number of taps kept per output row. Row 1 is the framework’s selected solution (NVE 0.549; as shipped, complex64 / int64 , 2.7

\times

more); row 2 is the cheapest point on its published front, so the gap is not an artifact of picking the largest variant. The last row is the simulator’s linker map, which exposes 8 704 B of the 16 kB IPPU .

Panel of Figure 2 — Fig. 1: The campaign as three metered phases. The agent writes its artifacts only in the agent lane: the evaluators above are pinned upstream code it is instructed not to edit, and the instruments below bind every artifact to an executable reference. Silicon appears once, at the end; facts measured there return to the knowledge base.

Panel of Figure 3 — Fig. 2: The evaluation chain behind every NVE . Only the shaded block is the agent’s; every other stage is the framework’s own code [ 1 ] , imported unmodified. Frames run in batches of eight until 50 block errors accumulate, capped at 1600 (Sec. V-B ).

Kernel	NVE	Cycles	vs. PoC	DMEM	PRAM
lmmse_poc	0.65	31 008 649	—	69.5%	49.0%
lmmse_opt	0.65	18 318	1693 $\times$	97.9%	50.5%
ep_poc	0.94	62 503 987	—	76.9%	51.0%
ep_opt	0.94	405 379	154 $\times$	100%	70.5%
mp_poc	1.09	248 238 967	—	83.6%	53.1%
mp_opt	1.09	232 847	1066 $\times$	95.8%	54.2%

TABLE II: The OTFS kernel portfolio. Cycles per frame, identical in simulator and on silicon (Sec. V-A ); NVE at the protocol’s resolution, with approximate 95% intervals of about

\pm

0.15 (Sec. V-B ).

\star

designed in this campaign.

Panel of Figure 5 — Fig. 3: Coded error rate versus measured silicon cycles per frame; the top axis converts cycles to time, the dashed vertical marks the 267 $\mu$ s frame budget. Dotted ties link each algorithm’s two versions (only ec2rich ’s is non-horizontal, 0.006 apart). The black dashed staircase is the Pareto front of the measured values. Vertical bars: approximate 95% NVE intervals of the optimized kernels (Sec. V-B ); cycles are exact. The three kernels near the front overlap in NVE ; EP , UAMP and MP lie above them and are dominated by ec_frozen_opt even at the interval level.

Algorithm	PoC	Opt	HW	Total
	Output tokens ( $10^{3}$ )
LMMSE	38.5	228.5	12.5	279.5
EP	41.2	387.4	12.5	441.0
MP	39.7	249.4	14.7	303.7
UAMP	47.7	432.0	32.4	512.0
EC (discovered)	52.5	307.2	13.5	373.2

TABLE III: Measured engineering effort per algorithm and phase: agent output tokens (

10^{3}

, incl. billed reasoning), deduplicated per API response.

Detector	lite (dB)	full (dB)	$\Delta_{\mathrm{red}}$ (dB)
UAMP	8.55	12.54	$+3.98$
MP	9.03	13.14	$+4.11$
EC (discovered)	7.92	12.30	$+4.38$
EP	8.58	13.08	$+4.50$
LMMSE	7.82	14.55	$+6.73$

TABLE IV: Link cost of the grid reduction: coded BLER-

10^{-1}

crossings of the upstream detectors through one chain at both operating points: lite (

8\times 4

, QPSK , codeword

n{=}64

) and full (

64\times 64

, 16- QAM ,

n{=}16\,384

; 3- vs 6-path channel). Pre-registered sweep,

\geq

50 block errors or 1600 frames per point;

\Delta_{\mathrm{red}}

= full

-

lite.

Hardware-Software Co-Design

Hardware-software co-design jointly shapes algorithms, software, and computing hardware to meet performance, energy, cost, and deployment constraints.

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Abstract

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