We present the framework of TACS-RF - a Tool-driven Agentic Circuit Synthesis of RF and mmWave modules. In this framework, a large-language-model (LLM) coding agent (Claude Opus 4.8) directly drives industry-standard electronic-design-automation (EDA) tools such as Cadence Virtuoso/Spectre, Calibre, Cadence EMX, and Ansys HFSS to design RF and mmWave modules. We validate the framework through the agentic design of a 240-251 GHz sub-THz transmitter in a 90 nm SiGe BiCMOS process. The agent semi-autonomously designed the sub-blocks including a 60 GHz push-push Colpitts VCO with second-harmonic extraction, multistage differential cascode power drivers, a push-push frequency doubler, a differential bowtie antenna, and all the interstage matching networks. The transmitter chain with parasitic-extracted devices and EM-verified passives delivers +5.1 to +6.3 dBm across an 11 GHz varactor-only tuning range, phase noise of -80 to -88 dBc/Hz at 1 MHz offset while consuming a DC power of 361 mW. We describe the agent-driven design flow and the resulting division of labor between human and agent, taking a step toward a "text-to-ASIC" future for designing RF/mmWave hardware.
Figures & tables
Fig. 1: An LLM-driven EDA workflow for RF and mmWave circuit design that integrates Cadence Virtuoso, EMX, HFSS/PyAEDT, and Calibre.
Fig. 2: Design flow of the sub-THz transmitter, demonstrating complete automation by the LLM agent from initial setup to the final AI-generated layout.
Fig. 3: A representative design guideline provided to the LLM-agent.
Fig. 4: Agent-designed 240–251 GHz transmitter. (a) Complete transmitter schematic in a 90 nm SiGe BiCMOS process. (b) Automated design results for the small signal inter-stage matching and achieved performance benchmarks. (c) Simulated performance of the 60 GHz VCO with second harmonic extraction. (d) Schematic and lumped model based performance optimization of the sub-THz transmitter across varying number of driver stages. (e) Simulations of the transmitter with 2 driver stages with EM extracted passives and RCC-extracted devices: output power ( Pout ) and phase noise (PN) at a 1 MHz offset across the varactor Vtune sweep. The operating frequency is limited by the varactor tuning range.
Fig. 5: TACS-RF framework performing EM simulations using Ansys HFSS and Cadence EMX. A representative transformer balun design in EMX: (a) layout and (b) extracted parameters. A 240 GHz antenna design in HFSS: (c) antenna layout, and (d) simulated input matching, gain, and directivity.
Reference
Process
fT/fmax
Frequency
Pout
Pdc
Phase Noise
(GHz)
[ 5 ] a
0.13 μ m SiGe
300/500
229–251 GHz
1–2 dBm
0.29 W
− 85 dBc/Hz @ 1 MHz
[ 6 ] b
55 nm SiGe
330/350
234–261 GHz
5.4–7.2 dBm
0.38 W
− 105 dBc/Hz @ 10 MHz
This work c
90 nm SiGe
300/350
240–251 GHz
5.1–6.3 dBm
0.36 W
− 88 d @ 1 MHz; − 108 d @ 10 MHz
a Push-push VCO + PA + doubler. b 120 GHz VCO + LO tree + doubler. c Push-push VCO + 2 PAs + doubler. d operating at 248 GHz.
TABLE I: Comparison With Prior Sub-THz SiGe Sources
Analog/RF circuits remain the critical interface between digital computation and the physical world, and emerging standards from Wi-Fi 7 to 6G place stringent demands on them, yet analog/RF design remains one of the most labor-intensive steps in chip development. We present RFChipAgent, a first-of-its-kind multi-agent flow of large language model (LLM) agents for end-to-end analog/RF circuit design automation, in which AI agents collaboratively orchestrate the complete design flow under human supervision. RFChipAgent is built around four technical pillars. First, a multimodal retrieval-augmented generation (RAG) subsystem with private per-document FAISS indexing extracts design knowledge from existing engineering documentation. Second, a topology agent drives topology selection, and a schematic and testbench agent automates circuit and testbench assembly. Third, a closed-loop hybrid circuit-sizing engine combines Tree-structured Parzen Estimator (TPE) and CMA-ES optimization, evaluating every candidate in a simulator-in-the-loop framework. Fourth, a trust-scored simulation database accumulates verified performance data and builds an adaptive optimization model that informs subsequent trials. We validate RFChipAgent on a family of GF22FDSOI 60 GHz wideband mm-wave low-noise amplifier (LNA) topologies, demonstrating automated topology generation, specification-driven design-space exploration, and simulator-guided optimization. Experimental results show substantial reductions in design effort while maintaining signoff-quality verification. This work establishes a foundation for LLM-driven multi-agent electronic design automation (EDA) for analog/RF circuits.
Large language models (LLMs) have driven rapid progress in electronic design automation (EDA), yet their application to radio-frequency (RF) circuit design remains limited by the scarcity of domain-specific datasets and standardized benchmarks. We present RF-Agent, which addresses this gap through textbook-driven knowledge distillation. A multi-agent Question-Thinking-Solution-Answer (QTSA) pipeline converts a subsection-level corpus from seven canonical RF textbooks into the first-of-its-kind RF-domain reasoning dataset (over 11,000 samples) with a dedicated multiple-choice benchmark. On this benchmark we study two adaptation strategies: supervised fine-tuning (SFT) and three retrieval-augmented generation (RAG) configurations (semantic, keyword, hybrid). Across multiple LLM families, domain-specific SFT significantly improves RF reasoning, especially for small and medium-sized models; among RAG configurations, semantic retrieval performs best, indicating embedding-based context alignment suits RF reasoning better than naive fusion. The dataset and benchmark provide a reusable foundation for future work on LLM-aided RF circuit design.
Yueqi Xing, Houbo He, Jolie Wang +5
ECE Department, Rice University, Houston, TX, USA · ECE Department, The George Washington University, Washington, D.C., USA
Driven by a rapid co-evolution of both harness and underlying models, LLM agents are improving at a dizzying pace. In our prior work (performed in Dec. 2025), we introduced "Design Conductor" (or just "Conductor"), a system capable of building a 5-stage Linux-capable RISC-V CPU in 12 hours. In this work, we introduce an updated multi-agent harness powered by frontier models released in April 2026, which is able to handle 80x larger tasks, at higher quality, fully autonomously. Following a brief introduction, we examine 4 designs that the system produced autonomously, including "VerTQ", an LLM inference accelerator which hard-wires support for TurboQuant in a 240-cycle pipeline, starting from the TurboQuant arXiv paper. VerTQ includes heavy compute processing, with 5129 FP16/32 units; the design was mapped to an FPGA at 125 MHz and consumes 5.7 mm^2 in TSMC 16FF (8 attention pipes). We review the key new characteristics that enabled these results. Finally, we analyze Design Conductor's token usage and other empirical characteristics, including its limitations.