Systemverilog Assertions

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3 papers in the last four weeks, against 1 the four weeks before. 0.0% of all new papers.

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EquivSVA: A Formally Verified Dataset of Behavioral Assertions Across Equivalent RTL Implementations
Sep 22, 2026FNU AditiSystemverilog Assertions Hierarchical Register Transfer Level Generation
Fabrication After Tool Failure: Tool-Augmented Agents Assert Values Their Tools Did Not Return
Sep 13, 2026Arham Sethi, Arsen Kenzhebayev, Saanvi Paturi +3Honesty Systemverilog Assertions
The Shishukunj International School · Haileybury Astana · UWCSEA East Campus +2
Watermarks Without Verification: AI Text Watermarking After the EU AI Act
Sep 10, 2026Alexander Nemecek, Vipin Chaudhary, Erman AydayAi-Generated Content Detection Watermarks
Case Western Reserve University
ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware
Sep 1, 2026Yuannuo Feng, Yizhe Chen, Wenshuai Yao +4Diffusion Models In-Memory Computing
School of Integrated Circuit Science and Engineering, Beihang University, Beijing, China · Zhicun Research Lab, Beijing, China · School of Integrated Circuits, Peking University, Beijing, China +1
Faithful Autoformalization of Natural Language Assertions
Jul 14, 2026Hongyi Liu, Madhusudan Parthasarathy, Adithya MuraliAutoformalization Systemverilog Assertions
University of Wisconsin-Madison · University of Illinois at Urbana-Champaign
Adversarial Social Epistemology for Assemblies of Humans and Large Language Models
Jul 8, 2026Mihnea C. Moldoveanu, Joel A. C. BaumEpistemic States AI Trustworthiness
University of Toronto
Code-Augur: Agentic Vulnerability Detection via Specification Inference
Jun 17, 2026Zhengxiong Luo, Mehtab Zafar, Dylan Wolff +1Vulnerable Code Systemverilog Assertions
National University of Singapore
HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification
Jun 9, 2026Maohua Nie, Jiang Zhu, Jingqun Zhang +5Formal Verification Systemverilog Assertions
University of Washington · Independent Researcher
CuriosAI Submission to the CASTLE Challenge at EgoVis 2026
May 27, 2026Yuto Kanda, Hayato Tanoue, Takayuki HoriChallenges Answer
SoftBank Corp.
ConVer: Using Contracts and Loop Invariant Synthesis for Scalable Formal Software Verification
May 26, 2026Muhammad A. A. Pirzada, Weiqi Wang, Yiannis Charalambous +2Formal Verification Probabilistic Model Checking
The University of Manchester · Manchester, UK
AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications
May 26, 2026Yuchao Wu, Wenji Fang, Jing Wang +3Systemverilog Assertions High-Level Synthesis
Hong Kong University of Science and Technology (HKUST)
SpecAlign: A Semantic Alignment Framework for SystemVerilog Assertion Generation
May 24, 2026Jaime Rafael Imperial, Hao ZhengSystemverilog Assertions High-Level Synthesis
Bellini College of Cybersecurity, AI, and Computing University of South Florida Tampa, USA
Towards a compositional semantics for quantitative confidence assessment in assurance arguments
May 21, 2026Benjamin Herd, Jessica Kelly, Jan Sabsch +1Confidence Calibration Confidence Estimation
Fraunhofer IKS · Munich, Germany · Luxoft GmbH +2
Reward-Weighted On-Policy Distillation with an Open Property-Equivalence Verifier for NL-to-SVA Generation
May 13, 2026Qingyun Zou, Yingze Li, Tianen Liu +2Systemverilog Assertions High-Level Synthesis
National University of Singapore
Safe Multi-Agent Behavior Must Be Maintained, Not Merely Asserted: Constraint Drift in LLM-Based Multi-Agent Systems
May 11, 2026Tianxiao Li, Yixing Ma, Haiquan Wen +4Safety Constraints Systemverilog Assertions
University of Liverpool, UK · University of Nottingham, UK · University of Tokyo, Japan +1
Autonomous FAIR Digital Objects: From Passive Assertions to Active Knowledge
May 11, 2026Zeyd Boukhers, Oya Beyan, Cong Yang +1Ontology Systemverilog Assertions
Fraunhofer Institute for Applied Information Technology FIT, Germany · University Hospital Cologne UKK, Cologne, Germany · University of Cologne, Faculty of Medicine and University Hospital Cologne, Cologne, Germany +2
Arcane: An Assertion Reduction Framework through Semantic Clustering and MCTS-Guided Rule Exploring
May 11, 2026Hongqin Lyu, Yonghao Wang, Zhiteng Chao +2Systemverilog Assertions High-Level Synthesis
State Key Lab of Processors, Institute of Computing Technology, CAS, Beijing, China · University of Chinese Academy of Sciences, Beijing, China
Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification
May 7, 2026Vaisakh Naduvodi Viswambharan, Keerthan Kopparam Radhakrishna, Deepak Narayan Gadde +1Formal Verification Systemverilog Assertions
Infineon Technologies Dresden AG & Co. KG, Germany · Infineon Technologies Semiconductor India Private Limited, India
Assert, don't describe: Linguistic features that shift LLM reasoning about animal welfare
Apr 30, 2026Jasmine Brazilek, Harper DunnLLM Reasoning Strategies Moral Reasoning
Compassion Aligned Machine Learning (CaML) · Independent researcher
When AI reviews science: Can we trust the referee?
Apr 26, 2026Jialiang Wang, Yuchen Liu, Hang Xu +7Peer Review Review
Department of Computer Science and Engineering, The Hong Kong University of Science and Technology, Hong Kong SAR 999077, China · Key Laboratory of New Generation Artificial Intelligence Technology and Its Interdisciplinary Applications, School of Computer Science and Engeering, Southeast University, Nanjing 210000, China · These authors contributed equally +2
How Large Language Models Balance Internal Knowledge with User and Document Assertions
Apr 24, 2026Shuowei Li, Haoxin Li, Wenda Chu +1Large Language Model Reliability Systemverilog Assertions
Santa Clara University · Nanyang Technological University · California Institute of Technology
No More Guessing: a Verifiable Gradient Inversion Attack in Federated Learning
Apr 16, 2026Francesco Diana, Chuan Xu, André Nusser +1Gradient-Based Attacks Federated Learning
Université Côte d’Azur, France · Inria, France · CNRS, France +1

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EquivSVA: A Formally Verified Dataset of Behavioral Assertions Across Equivalent RTL Implementations

FNU Aditi

Systemverilog Assertions Hierarchical Register Transfer Level Generation Register Transfer Level Test Generation

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Large language models are increasingly used to generate SystemVerilog Assertions from natural-language specifica- tions and register-transfer-level designs. Existing datasets and benchmarks support important goals such as large- scale training, formal evaluation, specification-to-assertion generation, and mutation-based testing. A complemen- tary need is to study whether a generated assertion cap- tures externally observable behavior or depends on inci- dental details of one RTL implementation. We present EquivSVA, a formally verified dataset organized around behavior families. Each family contains four structurally distinct RTL implementations of the same externally ob- servable behavior, shared interface-level gold properties, three controlled mutants, and formal-validation evidence. EquivSVA contains 120 behavior families across 12 cat- egories, 480 reference RTL implementations, 914 gold properties, and 360 mutants. Every final family passes a fixed 17-job validation suite covering RTL equivalence, gold-property proofs, property reachability, mutant dis- tinguishability, and gold-property checks on mutants. We also provide fixed family-safe train, development, and test splits. As a small demonstration of the analyses en- abled by the dataset, we evaluate the publicly released, Apache-2.0-licensed Qwen2.5-Coder-7B-Instruct model on the held-out test split. Of 293 interface-only generated properties, 93 are formally sound, and the number of sound properties varies across equivalent implementations for 14 of 24 test families. These results illustrate how behavior-family organization can support controlled stud- ies of assertion-generation robustness without requiring changes in intended functionality. The dataset, generators, validation scripts, and case-study artifacts are publicly released at https://github.com/aditigupta96/EquivSVA.

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