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4 papers in the last four weeks, against 1 the four weeks before. 0.0% of all new papers.

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  1. BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verification

    Sep 28, 2026Yuheng Wu, Berk Gokmen, Sujeeth Jinesh +5Self-Improving AgentsBehavioral Foundation Models

    Stanford University · Workato, Inc.

  2. ChipMEM: Verification-Grounded Memory for EDA Agents

    Sep 22, 2026Abdulrahman AlRabah, Joshua Mabry, Dilek Hakkani-Tür +4Electronic Design AutomationSemantic Memory

    University of Illinois Urbana-Champaign · NVIDIA · Cadence

  3. EquivSVA: A Formally Verified Dataset of Behavioral Assertions Across Equivalent RTL Implementations

    Sep 22, 2026FNU AditiSystemverilog AssertionsHierarchical Register Transfer Level Generation

  4. Trust, but Validate the Instrument: Auditing AI-Generated RTL Verification Plans on Authored Security-Regression Proxies

    Sep 17, 2026Hang Xiao, Chuhong Xu, Kainan Zhou +2Runtime EnforcementModel Auditing

    Fortinet, Inc. Sunnyvale, CA, USA · Sony Corporate of America San Jose, CA, USA · Google LLC Mountain View, CA, USA

  5. SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimization

    Aug 13, 2026Fangzhou Liu, Peiyi Han, Jiawei Liu +5Invariant SynthesisSynthesis

    Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong SAR.

  6. HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation

    Aug 7, 2026Tairan Cheng, Yi Liu, Dongsheng Zuo +6Register Transfer LevelHardware Efficiency

    The Chinese University of Hong Kong Hong Kong, China · Southeast University Nanjing, China

  7. RTLCurator: Label-Efficient Data Curation for RTL Generation

    Jul 31, 2026Siyang Cai, Cangyuan Li, Wenjing Chang +4Hierarchical Register Transfer Level GenerationRegister Transfer Level

    School of Advanced Interdisciplinary Sciences, University of Chinese Academy of Sciences, Beijing, China · CICS, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China · Computer Network Information Center, Chinese Academy of Sciences, Beijing, China +1

  8. Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair

    Jul 30, 2026Ha Trung TranFormal VerificationHigh-Level Synthesis

    Independent Researcher · Seattle, WA, USA

  9. ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents

    Jul 30, 2026Stef Cuyckens, Mihaela Jivanescu, Jun Yin +2Hierarchical Register Transfer Level GenerationRegister Transfer Level

    KU Leuven Leuven, Belgium · Nokia Bell Labs Antwerp, Belgium

  10. GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure

    Jul 28, 2026Xin Xin, Jincheng Lou, Junhui Li +11Formal VerificationRegister Transfer Level

    Tencent · School of Integrated Circuits, Peking University, Beijing · Southwest Jiaotong University +1

  11. Can AI Agents Really Complete RTL-to-GDS? Lessons from Benchmarking Tool-Interactive EDA Workflows

    Jul 20, 2026Jinyuan Deng, Zhengrui Chen, Xufeng Wei +4Electronic Design AutomationAgentic Workflow Design

    1Zhejiang University, China · 2ChipFlux, China

  12. RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm

    Jul 17, 2026Ziyan Guo, Wenji Fang, Wenkai Li +3Sequence ModelingRegister Transfer Level

    Hong Kong University of Science and Technology (HKUST)

  13. AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting

    Jun 16, 2026Yiting Wang, Chenhui Deng, Chia-Tung Ho +6Hierarchical Register Transfer Level GenerationField-Programmable Gate Arrays

    University of Maryland, College Park · NVIDIA

  14. Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement

    Jun 16, 2026You Li, Samuel Mandell, David Z. PanEdge HardwareRegister Transfer Level

    The University of Texas at Austin · USA

  15. LLM4RTL: Tool-Assisted LLM for RTL Generation

    Jun 13, 2026Jing Jin, Robert Chu, Ning Yan +1High-Level SynthesisRegister Transfer Level

    UC Riverside · Riverside, CA, USA · Futurewei +1

  16. Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation

    Jun 11, 2026En-Ming Huang, Yu-Hung Kao, Ren-Hao Deng +10Hierarchical Register Transfer Level GenerationTest Generation

    National Taiwan University · Academia Sinica · Harvard University

  17. RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models

    Jun 8, 2026Jing Wang, Shang Liu, Wenji Fang +3Register Transfer LevelLarge Language Model Benchmarks

    Hong Kong University of Science and Technology

  18. CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

    Jun 4, 2026Mohammad Akyash, Nowfel Mashnoor, Kimia Azar +1Hierarchical Register Transfer Level GenerationRegister Transfer Level

    Department of Electrical and Computer Engineering (ECE), University of Central Florida, Orlando, FL 32816, USA

  19. Alpha-RTL: Test-Time Training for RTL Hardware Optimization

    Jun 3, 2026Peilong Zhou, Zhirong Chen, Cangyuan Li +4Hierarchical Register Transfer Level GenerationRegister Transfer Level

    1SKLP, Institute of Computing Technology, Chinese Academy of Sciences · University of the Chinese Academy of Sciences · School of Advanced Interdisciplinary Sciences

  20. EstRTL: Functional Estimation Guided RTL Code Generation

    Jun 1, 2026Qi Xiong, Renzhi Chen, Bowei Wang +3Hierarchical Register Transfer Level GenerationRegister Transfer Level

    College of Computer Science and Technology, National University of Defense Technology, Changsha, China · Defense Innovation Institute, Academy of Military Science (AMS), Beijing, China · School of Computer Science and Technology, Shandong University, Qingdao, China +2

  21. UniRTL: Unifying Code and Graph for Robust RTL Representation Learning

    May 29, 2026Yi Liu, Hongji Zhang, Lei Chen +2Hierarchical Register Transfer Level GenerationRegister Transfer Level

    Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong SAR · Noah’s Ark Lab, Huawei, Hong Kong SAR

  22. AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications

    May 26, 2026Yuchao Wu, Wenji Fang, Jing Wang +3Systemverilog AssertionsHigh-Level Synthesis

    Hong Kong University of Science and Technology (HKUST)

  23. Trace2Skill: Verifier-Guided Skill Evolution for Long-Context EDA Agents

    May 20, 2026Zijian Du, Nathaniel PinckneyHigh-Level SynthesisSkill Evolution

    NVIDIA · Santa Clara, CA, USA

  24. RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision

    May 15, 2026Jing Wang, Shang Liu, Hangan Zhou +1Register Transfer LevelLarge Language Model Benchmarks

    Hong Kong University of Science and Technology · Clear Water Bay, Hong Kong

  25. ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation

    May 13, 2026Zhongkai Yu, Yichen Lin, Chenyang Zhou +12Hierarchical Register Transfer Level GenerationRegister Transfer Level

    UCSD · Columbia University

  26. Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification

    May 7, 2026Vaisakh Naduvodi Viswambharan, Keerthan Kopparam Radhakrishna, Deepak Narayan Gadde +1Formal VerificationSystemverilog Assertions

    Infineon Technologies Dresden AG & Co. KG, Germany · Infineon Technologies Semiconductor India Private Limited, India

  27. RuC: HDL-Agnostic Rule Completion Benchmark Generation

    Apr 30, 2026Arnau Ayguadé Domingo, Miquel Alberti-Binimelis, Cristian Gutierrez-Gomez +5Code CompletionRegister Transfer Level

    Barcelona Supercomputing Center · Universitat Polit`ecnica de Catalunya

  28. How LLMs Fail and Generalize in RTL Coding for Hardware Design?

    Apr 26, 2026Guan-Ting Liu, Chao-Han Huck Yang, Chenhui Deng +3Register Transfer LevelLarge Language Models Fail

    NVIDIA Research

  29. TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog

    Apr 26, 2026Armin Abdollahi, Negin Ashrafi, Mehdi Kamal +1High-Level SynthesisRegister Transfer Level

    University of Southern California Los Angeles, CA, USA

  30. ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration

    Apr 21, 2026Cagri EryilmazRegister Transfer LevelLlm-Driven Code Synthesis

    ChipCraftX San Francisco, CA

  31. AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning

    Apr 20, 2026Chongxiao Li, Pengwei Jin, Di Huang +14Prompt OptimizationOptimal Power Shutoff

    State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China · University of Chinese Academy of Sciences, Beijing, China · University of Science and Technology of China, Hefei, China +1

  32. Clover: A Neural-Symbolic Agentic Harness with Stochastic Tree-of-Thoughts for Verified RTL Repair

    Apr 19, 2026Zizhang Luo, Yansong Xu, Runlin Guo +6Automated Program RepairRepair

    Peking University

  33. Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation

    Apr 18, 2026Minghao Shao, Zeng Wang, Weimin Fu +5Large Language Model BenchmarksRegister Transfer Level

    NYU Tandon School of Engineering, USA · Kansas State University, USA · NYU Abu Dhabi, UAE

  34. HYPERHEURIST: A Simulated Annealing-Based Control Framework for LLM-Driven Code Generation in Optimized Hardware Design

    Apr 17, 2026Shiva Ahir, Prajna Bhat, Alex DoboliRegister Transfer LevelAutomated Heuristic Design

    Department of ECE

  35. COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation

    Apr 16, 2026Heng Ping, Peiyu Zhang, Shixuan Li +5Register Transfer LevelCo-Evolution

    University of Southern California United States

  36. Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement

    Apr 16, 2026Wenji Fang, Yao Lu, Shang Liu +5Hierarchical Register Transfer Level GenerationRegister Transfer Level

    Hong Kong University of Science and Technology (HKUST)

  37. VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs

    Apr 16, 2026Sazzadul Islam, Tasnim Tabassum, Hao ZhengHigh-Level SynthesisHierarchical Register Transfer Level Generation

    Dept. of Computer Science & Eng. University of South Florida Tampa, Florida, United States