cs.LGMar 25, 2026

Can an Actor-Critic Optimization Framework Improve Analog Design?

Authors: Sounak Dutta, Fin Amin, Sushil Panda, Jonathan Rabe, Yuejiang Wen, Paul Franzon

Organizations: North Carolina State University, Department of Electrical and Computer Engineering, Raleigh, North Carolina, USA

Read PDF
Ask AI
Cite

Copy citation

DOINot available for this paper

Abstract

Analog design often slows down because even small changes to device sizes or biases require expensive simulation cycles, and high-quality solutions typically occupy only a narrow part of a very large search space. While existing optimizers reduce some of this burden, they largely operate without the kind of judgment designers use when deciding where to search next. This paper presents an actor-critic optimization framework (ACOF) for analog sizing that brings that form of guidance into the loop. Rather than treating optimization as a purely black-box search problem, ACOF separates the roles of proposal and evaluation: an actor suggests promising regions of the design space, while a critic reviews those choices, enforces design legality, and redirects the search when progress is hampered. This structure preserves compatibility with standard simulator-based flows while making the search process more deliberate, stable, and interpretable. Across our test circuits, ACOF improves the top-10 figure of merit by an average of 38.9% over the strongest competing baseline and reduces regret by an average of 24.7%, with peak gains of 70.5% in FoM and 42.2% lower regret on individual circuits. By combining iterative reasoning with simulation-driven search, the framework offers a more transparent path toward automated analog sizing across challenging design spaces.

Figures & tables

Figure 1. Example of interactions between our actor and critic during analog sizing optimization. Our framework defines a closed-loop optimization process that alternates between proposal, audit, search, and reflection.
Figure 2. An overview of our actor–critic optimization framework (ACOF). At each time step, nn , the actor proposes a candidate search region Ω~n\tilde{\Omega}_{n} , the critic adjusts it to a PDK-legal region Ωn+\Omega_{n}^{+} , BO selects candidates x∈Ωn+x\in\Omega_{n}^{+} for simulation, and simulator outcomes are summarized into ene_{n} for the next round. ACOF is agnostic to the specific choice of BO.
 Top-10 Design QualityReliability (%)Exploration/Exploitation
 MethodGain (dB) ↑\uparrowUGBW (MHz) ↑\uparrowPM (deg) ↑\uparrowPower (mW) ↓\downarrowFoM ↑\uparrowSim. Valid ↑\uparrowPhys. Feasible ↑\uparrowRegions ↑\uparrowRegret ↓\downarrow
130nm 12 ParamsTarget Spec.85.00900.00100.000.5540.00----
[0.4pt/1.2pt]ACOF83.65 0.64785.30 39.71101.35 1.130.658 0.045-0.19 0.0197.0 0.186.2 1.42.0 0.00.25 0.01
 LEDRO83.15 0.55717.63 45.51111.89 0.740.657 0.029-0.24 0.0295.4 0.978.9 1.82.7 0.30.30 0.01
 Pure-BO76.24 1.45673.92 22.65128.23 3.270.587 0.014-0.39 0.0281.0 0.326.9 0.13.0 0.80.37 0.02
 Human Expert72.77851.48173.590.821-0.45----
Table 1. Results across the four test circuits. Each circuit forms one multi-row block at left. Values are mean with standard errors in subscripts. Bold indicates the best baseline method within each circuit and metric. Qwen was used as the LLM.
Figure 3. UMAP projections of the sizing parameters illustrate how the design space was explored over optimization rounds. To aid visualization, we outlined regions being explored in the current rounds in red and rendered the cumulative explored designs from past rounds in gray. ACOF judiciously explores the design space by targeting regions corresponding to high performance–as indicated by the higher round-wise Avg and Max FoM. Our technique successfully explored the regions above UMAP Component 2>1\texttt{UMAP Component 2}>1 . On the other hand, the baselines were apprehensive of exploration and achieved worse FoMs.
Figure 4. The circuit schematics of our benchmarks. For an OpAmp, gain, bandwidth, phase margin, and power are coupled design specifications. Higher DC gain can introduce additional poles; this affects phase margin. Also, improving UGBW usually requires higher bias current and therefore higher power. The design must therefore balance gain, UGBW, power, and phase margin.
Figure 5. Exponentially-smoothed FoM trajectories for the 180nm 21-parameter folded-cascode benchmark using variants of GPT as the LLM. Subcaptions report the across-run mean of the per-run top-10 mean FoM. Optimization steps for the LLM-based methods begin at 200 because both are initialized with C0=200\mathcal{C}_{0}=200 seed designs generated by Pure-BO. After initialization, the LLM-based methods update the optimization ranges every 100 steps.
ModelMethodTop-10 FoM ↑\uparrowPhys. Feasible (%) ↑\uparrowRegret ↓\downarrow
GPT-4o MiniACOF-0.359 0.01867.1 3.50.395 0.019
LEDRO-0.643 0.01537.8 2.30.579 0.021
GPT-5ACOF-0.271 0.02499.4 0.00.313 0.019
LEDRO-0.319 0.03580.9 8.90.381 0.024
Table 2. Results on the 180nm 21-parameter folded-cascode benchmark using variants of GPT as the LLM.
More in this topic

Analog Circuit Sizing

See all 13 papers

Explore similar work

CardsList
Sep 22, 2026

AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing

Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled technologies. Although recent large language model (LLM)-based methods show promise in improving sample efficiency and interpretability, existing approaches often lack explicit circuit-topology understanding and are mainly evaluated on relatively simple analog building blocks. This paper presents a multi-agent LLM-based framework for complex analog circuit sizing. The proposed framework first analyzes the circuit topology and decomposes the netlist into functional blocks and substructures. It also extracts lightweight design knowledge for reuse. Based on the extracted topology and knowledge, a planner coordinates multiple role-specialized sizing agents to update design variables and achieve global performance specifications. This workflow mimics the collaborative process of an expert analog design team and provides a structured, interpretable, and simulation-driven optimization procedure. The framework was validated on eight circuits, with the largest design containing up to 55 transistors and 60 sizing variables. Notably, for the LDO benchmark, the proposed method achieved a 60% success rate with an average of 83 iterations, where classical optimizers failed to find feasible solutions. Further, ablation studies demonstrate that topology understanding, design-knowledge infusion, and agent specialization provide complementary benefits. The source code is available to support reproducibility.

Yijia Hao, Pratibha Verma, Dongxu Guo +4

Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, UK · Department of Electrical Engineering, Indian Institute of Technology Indore, India · School of Informatics, The University of Edinburgh, UK +1

Large Language Model-Guided OptimizationElectronic Design AutomationAnalog Circuit SizingMulti-Agent LLMsLLM Agent Planning
AskPDF
Mar 25, 2026

AnalogAgent: Self-Improving Analog Circuit Design Automation with LLM Agents

Recent advances in large language models (LLMs) suggest strong potential for automating analog circuit design. Yet most LLM-based approaches rely on a single-model loop of generation, diagnosis, and correction, which favors succinct summaries over domain-specific insight and suffers from context attrition that erases critical technical details. To address these limitations, we propose AnalogAgent, a training-free agentic framework that integrates an LLM-based multi-agent system (MAS) with self-evolving memory (SEM) for analog circuit design automation. AnalogAgent coordinates a Code Generator, Design Optimizer, and Knowledge Curator to distill execution feedback into an adaptive playbook in SEM and retrieve targeted guidance for subsequent generation, enabling cross-task transfer without additional expert feedback, databases, or libraries. Across established benchmarks, AnalogAgent achieves 92% Pass@1 with Gemini and 97.4% Pass@1 with GPT-5. Moreover, with compact models (e.g., Qwen-8B), it yields a +48.8% average Pass@1 gain across tasks and reaches 72.1% Pass@1 overall, indicating that AnalogAgent substantially strengthens open-weight models for high-quality analog circuit design automation.

Zhixuan Bao, Zhuoyi Lin, Jiageng Wang +5

Nanyang Technological University Singapore · Institute for Infocomm Research Singapore · Institute of Microelectronics Singapore +2

Electronic Design AutomationLLM Agent Self-ImprovementMemory-Augmented Language Model AgentsMulti-Agent LLM Systems
AskPDF
Apr 8, 2026

A Self-Calibrating Framework for Analog Circuit Sizing Using LLM-Derived Analytical Equations

We present a design automation framework for analog circuit sizing that produces calibrated, topology-specific analytical equations from raw circuit netlists. A large language model (LLM) derives a complete Python sizing function in which each device dimension is traceable to a specific design rationale - a form of interpretable output absent from existing optimization-based and LLM-based sizing methods. A deterministic calibration loop extracts process-dependent parameters from a single DC operating point simulation, while a prediction-error feedback mechanism compensates for analytical inaccuracies. We validate the framework on circuits ranging from 6 to 30 transistors - spanning single-stage, current-mirror (simple and cascoded), folded-cascode, gain-boosted folded-cascode, two-stage Miller-compensated, nested-Miller-compensated, and complementary class-AB output topologies - across six process nodes from 32 nm to 180 nm. On matched-specification benchmarks, including the class-AB opamp case, the framework converges within a few simulations. Despite large initial prediction errors, convergence depends on the measurement-feedback architecture, not prediction accuracy. The one-shot calibration automatically captures process-dependent variations, enabling cross-node portability without modification, retraining, or per-process characterization.

Antonio J. Bujana, Aydin I. Karsilayan

Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA. · Department of Engineering, Benedictine College, Atchison, KS, USA.

Electronic Design AutomationAnalog Circuit Sizing
AskPDF