Hardware-Software Co-Design

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1 paper in the last four weeks, down 75% on the four weeks before. 0.0% of all new papers.

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Latest papers 46

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LLM-Driven Design Space Exploration of FPGA-based Accelerators
May 7, 2026Vinamra Sharma, Xingjian Fu, Jude Haris +1Large Language Model-Guided Optimization Electronic Design Automation
School of Computing Science, University of Glasgow, Scotland, UK
TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
May 6, 2026Chang Meng, Hanyu Wang, Yuyang Ye +3AI Accelerator Inference Energy-Efficient ML
Eindhoven University of Technology Eindhoven, The Netherlands · University of California, Los Angeles Los Angeles, USA · Chinese University of Hong Kong Hong Kong, China +2
ViM-Q: Scalable Algorithm-Hardware Co-Design for Vision Mamba Model Inference on FPGA
May 3, 2026Shengzhe Lyu, Yuhan She, Patrick S. Y. Hung +2Efficient Neural Network Inference Edge Inference
City University of Hong Kong, Hong Kong
SwiftChannel: Algorithm-Hardware Co-Design for Deep Learning-Based 5G Channel Estimation
May 3, 2026Shengzhe Lyu, Yuhan She, Di Duan +5Wireless Communications Hardware-Software Co-Design
Department of Computer Science, City University of Hong Kong, Hong Kong · Department of Electrical Engineering, City University of Hong Kong, Hong Kong · Department of Information Engineering, The Chinese University of Hong Kong, Hong Kong +2
Assistants, Not Architects: The Role of LLMs in Networked Systems Design
Apr 28, 2026Pratyush Sahu, Rahul Bothra, Venkat Arun +3Satisfiability Modulo Theories Hardware-Software Co-Design
Georgia Tech · UIUC · UT Austin +1
DenseScout: Algorithm-System Co-design for Budgeted Tiny Object Selection on Edge Platforms
Apr 28, 2026Xiong Zhouzhi, Zimo Zeng, Yi Chen +3Small Object Detection Edge Inference
College of Electrical Engineering, Zhejiang University, Hangzhou, China
Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models
Apr 23, 2026Muhammad Shafique, Abdul Basit, Muhammad Abdullah Hanif +3Model Compression Efficient Multimodal Inference
eBRAIN Lab, New York University (NYU) Abu Dhabi, Abu Dhabi, United Arab Emirates
M100: An Orchestrated Dataflow Architecture Powering General AI Computing
Apr 20, 2026Yan Xie, Changkui Mao, Changsong Wu +34AI Accelerator Inference LLM Inference Acceleration
Li Auto
Identifying and Exploiting Structure in Robot Co-Design
Apr 13, 2026Apoorv Vaish, Oliver BrockRobot Morphology-Control Co-Design Robotic Manipulation
Robotics and Biology Laboratory, Technische Universität Berlin · Science of Intelligence (SCIoI), Cluster of Excellence, Berlin · Robotics Institute Germany (RIG)
CableTract: A Co-Designed Cable-Driven Field Robot for Low-Compaction, Off-Grid Capable Agriculture
Apr 10, 2026Ozgur YilmazRobotics Hardware-Software Co-Design
Adana Science and Technology University, Adana, Türkiye
A Co-Design Framework for High-Performance Jumping of a Five-Bar Monoped with Actuator Optimization
Apr 7, 2026Aastha Mishra, Aman Singh, Shishir KolathayaLegged Robotics Mechanism Design
Department of Cyber-Physical Systems (CPS), Indian Institute of Science (IISc), Bengaluru, India.
Amanous: Distribution-Switching for Superhuman Piano Density on Disklavier
Feb 28, 2026Joonhyung BaeSymbolic Music Generation Hardware-Software Co-Design
Graduate School of Culture Technology KAIST (Korea Advanced Institute of Science and Technology) Daejeon, South Korea
Soft yet Effective Robots via Holistic Co-Design
Apr 20, 2025Maximilian Stölzle, Niccolò Pagliarani, Francesco Stella +6Hardware-Software Co-Design Soft Robotics
Laboratory for Information & Decision Systems, Massachusetts Institute of Technology, Cambridge, 02139, MA, USA. · Cognitive Robotics, Delft University of Technology, Mekelweg 2, Delft, 2628 CD, Netherlands. · Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, Cambridge, 02139, MA, USA. +4
Accelerating Stateful Network Applications with Performance Prediction on SoC SmartNICs
Oct 29, 2024Shaoke Xi, Jiaqi Gao, Fuliang Li +2Hardware-Software Co-Design
Alibaba Cloud · Northeastern University, China · Harvard University
Context-Aware System Synthesis, Task Assignment, and Routing
Jun 14, 2017Jason Ziglar, Ryan Williams, Alfred WicksCombinatorial Optimization Robotics
FP8 is All You Need (Part 2): Full-FP64 3-D FFT on FP8-Generation Tensor CoresThe Integer-Epilogue Wall and the Minimal Hardware That Would Remove It
Date pendingSatoshi MatsuokaGPU Kernel Optimization GPU Acceleration
Director, RIKEN Center for Computational Science (R-CCS), Kobe, Hyogo, Japan

May 7, 2026, cs.ARJ/K move · Enter open · S save

LLM-Driven Design Space Exploration of FPGA-based Accelerators

Vinamra Sharma, Xingjian Fu, Jude Haris, José Cano

School of Computing Science, University of Glasgow, Scotland, UK

Large Language Model-Guided Optimization Electronic Design Automation Hardware-Software Co-Design FPGA-Based Neural Network Acceleration

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Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompassing architectural parameters, dataflow strategies, and memory hierarchies, making the process time-consuming and resource-intensive. While the SECDA methodology enables rapid hardware-software co-design of accelerators through SystemC simulation and FPGA execution, identifying optimal accelerator configurations still requires substantial manual effort and domain expertise. This work presents SECDA-DSE, a framework that integrates Large Language Models (LLMs) into the SECDA ecosystem, comprising tools built around SECDA to automate the design space exploration (DSE) of FPGA-based accelerators. SECDA-DSE combines a structured DSE Explorer for generating accelerator configurations with an LLM Stack that performs reasoning-guided exploration using retrieval-augmented generation and chain-of-thought prompting, alongside a feedback loop that enables reinforced fine-tuning for continuous improvement. We demonstrate the feasibility of SECDA-DSE through an initial high-level synthesis based evaluation of a generated accelerator design that meets synthesis timing and resource constraints on an Zynq-7000 FPGA.

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