Signal Temporal Logic
Also known as STL
Overview
Signal Temporal Logic expresses requirements about how signals should behave over time, such as reaching a region within a deadline or avoiding hazards until a task is complete. Researchers use quantitative robustness scores, differentiable monitors, automata, and mixed-integer or reachability methods to learn specifications and synthesize or verify plans and controllers. Language models and vision systems are also being connected to STL so people can describe tasks in natural language or video and obtain inspectable formal requirements. A central challenge is balancing expressive specifications and reliable guarantees with computational cost, especially for continuous-time behavior, uncertainty, and imperfect translations.
Latest papers
34 papers4 papers in the last four weeks, down 20% on the four weeks before. 0.0% of all new papers.