Wafer-Level Etch Spatial Profiling for Process Monitoring from Time-Series with Time-LLM

Hyunwoo Kim; Munyoung Lee; Seung Hyub Jeon; Kyu Sung Lee

stat.APMar 24, 2026

Wafer-Level Etch Spatial Profiling for Process Monitoring from Time-Series with Time-LLM

Authors: Hyunwoo Kim, Munyoung Lee, Seung Hyub Jeon, Kyu Sung Lee

Organizations: Electronics and Telecommunications Research Institute, Daejeon, Republic of Korea

Abstract

Understanding wafer-level spatial variations from in-situ process signals is essential for advanced plasma etching process monitoring. While most data-driven approaches focus on scalar indicators such as average etch rate, actual process quality is determined by complex two-dimensional spatial distributions across the wafer. This paper presents a spatial regression model that predicts wafer-level etch depth distributions directly from multichannel in-situ process time series. We propose a Time-LLM-based spatial regression model that extends LLM reprogramming from conventional time-series forecasting to wafer-level spatial estimation by redesigning the input embedding and output projection. Using the BOSCH plasma-etching dataset, we demonstrate stable performance under data-limited conditions, supporting the feasibility of LLM-based reprogramming for wafer-level spatial monitoring.

Figures & tables

Fig. 1 : Overall architecture of the Time-LLM framework, reproduced from [ 7 ] .

Panel of Figure 2 — Fig. 2 : Example in-situ and ex-situ data from the BOSCH DRIE dataset: (a) gas flow, (b) RF power, (c) heater temperature, (d) OES intensity, and (e) wafer-level etch depth profile.

MSE (shape)
$L_{p}$	$S$	$N_{T}{=}3000$	$N_{T}{=}6000$	$N_{T}{=}9000$	$N_{T}{=}12000$
$32$	$16$	$0.42\pm 0.33$	$0.73\pm 0.41$	$0.51\pm 0.21$	$\mathbf{0.18\pm 0.10}$
$48$	$24$	$0.57\pm 0.35$	$0.37\pm 0.18$	$0.59\pm 0.28$	$0.44\pm 0.44$
$64$	$32$	$0.65\pm 0.41$	$0.53\pm 0.40$	$0.42\pm 0.12$	$0.46\pm 0.20$
MSE (mean)
$L_{p}$	$S$	$N_{T}{=}3000$	$N_{T}{=}6000$	$N_{T}{=}9000$	$N_{T}{=}12000$

TABLE I : 10-fold cross-validation errors (mean

\pm

std) for different patch length, stride, and sequence length.

$N_{\mathrm{oes}}$	$N_{\mathrm{c}}$	MSE (shape)	MSE (mean)	MAE (etch)
12	37	$1.11\pm 0.98$	$2.60\pm 3.76$	$1.31\pm 0.77$
24	49	$0.42\pm 0.22$	$3.80\pm 3.62$	$1.52\pm 0.73$
48	73	$0.37\pm 0.18$	$\mathbf{2.28\pm 2.00}$	$\mathbf{1.25\pm 0.51}$
72	97	$\mathbf{0.23\pm 0.08}$	$2.69\pm 2.31$	$1.36\pm 0.56$

TABLE II : 10-fold cross-validation errors (mean

\pm

std) for different numbers of OES channels.

Backbone	L	Ch	MSE (shape)	MSE (mean)	MAE (etch)
LLaMA	12	49	$\mathbf{0.19\pm 0.07}$	$3.20\pm 2.58$	$1.42\pm 0.56$
LLaMA	6	49	$0.22\pm 0.07$	$\mathbf{2.89\pm 2.14}$	$\mathbf{1.41\pm 0.49}$
LLaMA	6	73	$0.26\pm 0.14$	$3.23\pm 2.87$	$1.50\pm 0.62$
GPT2	12	73	$0.33\pm 0.13$	$3.59\pm 1.92$	$1.53\pm 0.43$
GPT2	6	73	$0.53\pm 0.40$	$3.70\pm 3.29$	$1.53\pm 0.71$
Global Mean Baseline			$12.91\pm 0.37$	$0.16\pm 0.07$	$2.97\pm 0.04$

TABLE III : 10-fold cross-validation errors (mean

\pm

std) for different model backbones and input channel configurations.

Semiconductor Manufacturing

Semiconductor manufacturing uses process engineering, metrology, and automation to make chips reliably, improve yield, and meet tight device requirements.

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Real-to-Sim Calibration of Bosch Etching Simulators with Few-Shot XSEM Data and Hybrid Search

Xinyu Jia, Jainil Shah, Rahul Tripathi, Vijay Gupta+1

Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana, USA · Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana, USA · Micron Semiconductor Asia Operations Pte. Ltd., 1 North Coast Drive, Singapore, 757432, Singapore

Real-to-Sim Transfer Semiconductor Manufacturing

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The Bosch process is widely used in MEMS and TSV fabrication, but accurate prediction of etching outcomes remains difficult without calibration against real measurements, which are sparse and costly to obtain. This work presents a few-shot real-to-sim calibration framework that decouples simulator parameters from direct process variables to infer a recipe-specific simulator parameter vector from sparse measurements, enabling reliable prediction of etch depth and sidewall angle under held-out process conditions. We first formulate Bosch profile prediction as a few-shot real-to-sim calibration problem, where a small set of real XSEM measurements is used to identify a recipe-specific ViennaPS parameter vector

z_r^*

that minimizes the discrepancy between simulated and measured etch depth and sidewall angle. To search this parameter space efficiently, the framework combines local exploration, LLM-guided candidate generation, and XGBoost-based surrogate screening, while retaining ViennaPS simulation as the final verification step for each selected candidate. Experiments on two Bosch etching recipes show that the proposed framework accurately predicts held-out etching results, achieving normalized global errors of 0.340 and 0.249 for the 2 recipes respectively.

Abstract

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