Agent Factories for High Level Synthesis: How Far Can General-Purpose Coding Agents Go in Hardware Optimization?

Abhishek Bhandwaldar; Mihir Choudhury; Ruchir Puri; Akash Srivastava

cs.AIMar 26, 2026

Agent Factories for High Level Synthesis: How Far Can General-Purpose Coding Agents Go in Hardware Optimization?

Authors: Abhishek Bhandwaldar, Mihir Choudhury, Ruchir Puri, Akash Srivastava

Organizations: IBM Corporation

Abstract

We present an empirical study of how far general-purpose coding agents -- without hardware-specific training -- can optimize hardware designs from high-level algorithmic specifications. We introduce an agent factory, a two-stage pipeline that constructs and coordinates multiple autonomous optimization agents. In Stage1, the pipeline decomposes a design into sub-kernels, independently optimizes each using pragma and code-level transformations, and formulates an Integer Linear Program (ILP) to assemble globally promising configurations under an area constraint. In Stage2, it launches $N$ expert agents over the top ILP solutions, each exploring cross-function optimizations such as pragma recombination, loop fusion, and memory restructuring that are not captured by sub-kernel decomposition. We evaluate the approach on 12 kernels from HLS-Eval and Rodinia-HLS using Claude Code (Opus~4.5/4.6) with AMD Vitis HLS. Scaling from 1 to 10 agents yields a mean $8.27\times$ speedup over baseline, with larger gains on harder benchmarks: streamcluster exceeds $20\times$ and kmeans reaches approximately $10\times$ . Across benchmarks, agents consistently rediscover known hardware optimization patterns without domain-specific training, and the best designs often do not originate from top-ranked ILP candidates, indicating that global optimization exposes improvements missed by sub-kernel search. These results establish agent scaling as a practical and effective axis for HLS optimization.

Figures & tables

Fig. 1: Two-stage agent-based pipeline for HLS design space exploration. Given an input design

\mathcal{D}

, a coordinator agent extracts the function call graph

G

and spawns one optimizer agent per sub-function

f_{1},\dots,f_{K}

. Variants are evaluated for correctness and synthesized to obtain (latency, area) pairs. An ILP solver then selects the top-

N

combinations

\mathcal{S}=\{s_{1},\dots,s_{N}\}

that minimize total latency subject to the area budget. In Stage 2,

N

exploration agents each start from a candidate solution and iteratively apply design-wide optimization paths, to produce the final optimized design

\mathcal{D}^{*}

Variant	Strategy
$v_{k}^{0}$	Baseline: synthesize unmodified code
$v_{k}^{1}$	Conservative: minimal pragmas, low area
$v_{k}^{2,3}$	Pipeline: PIPELINE II $\in\{1,2,4\}$
$v_{k}^{4,5}$	Aggressive: pipeline + partial/full UNROLL
$v_{k}^{6}$	Alternate: ARRAY_PARTITION , INLINE ,
	closed-form rewrites

TABLE I: Variant exploration strategy per sub-function.

Fig. 2: Pareto front results for all twelve benchmarks under agent scaling (

N\in\{1,2,4,8,10\}

). Each subplot shows speedup over baseline (y-axis) versus area (x-axis). Increasing the number of agents extends the Pareto front toward lower latency and more favorable area–latency trade-offs across most benchmarks, with the strongest gains on harder problems such as streamcluster, leukocyte, and NW.

	1 $\to$ 2	2 $\to$ 4	4 $\to$ 8	8 $\to$ 10
Speedup	4.31 $\times$ (+5.9%)	4.92 $\times$ (+14.2%)	7.07 $\times$ (+43.7%)	6.53 $\times$ (-7.6%)

TABLE II: Mean speedup over baseline as agents scale

DFG	Agent-formulated ILP & constraints
	$\min L_{iter}\cdot Loop\_count$ s.t. $L_{iter}\geq L_{F}+L_{O},\;L_{iter}\geq 2L_{F},\;L_{iter}\geq L_{E}+L_{F}$ $\sum_{v}x_{v}=1,\;\sum_{v}A_{v}x_{v}\leq A_{budget},\;x_{v}\in\{0,1\}$ One variant per function; $A_{v}$ is variant area.
	$\min 5(M_{FO}+2L_{E})$ s.t. $M_{FO}\geq L_{F},\;M_{FO}\geq L_{O}$ $\sum_{v}x_{v}=1,\;\sum_{v}A_{v}x_{v}\leq A_{budget},\;x_{v}\in\{0,1\}$ $L_{F},L_{O}$ denote latencies of F and O.
	$\min(L_{FM}+L_{TB}+L_{RS})$ $\sum_{v}x_{v}=1,\;\sum_{v}A_{v}x_{v}\leq A_{budget},\;x_{v}\in\{0,1\}$ $L_{FM},L_{TB},L_{RS}$ denote module latencies.
	$\min 11L_{ARK}+10L_{SB}+10L_{SR}+9L_{MC}+L_{KE}+L_{INIT}$ $\sum_{v}x_{v}=1,\;\sum_{v}A_{v}x_{v}\leq A_{budget},\;x_{v}\in\{0,1\}$ $L_{*}$ denotes module latency.

TABLE III: The agent analyzes data flow graphs and automatically formulates ILP constraints to minimize latency under an area budget. Dataflow graph borrowed from [ 12 ] .

Fig. 3: Latency improvement factor over baseline versus number of expert agents across six benchmarks. Improvements range from 1.4 $\times$ to 14.5 $\times$ and generally increase with agent count, typically plateauing after four agents.

Appendix figures & tables1 asset

Supplementary material from the paper’s appendix.

Appendix

Fig. 4: Average Inference cost of agent scaling. Each session is combination of Opus 4.5/4.6.

Electronic Design Automation

Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.

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Can Agents Design Better Chips with a Higher Level Abstraction?

Zijian Ding, Yang Zou, Yizhou Sun, Jason Cong

UCLA Los Angeles, CA, USA

Electronic Design Automation LLM Agent Workflow Optimization

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Large Language Model (LLM) agents are increasingly being explored for chip design, but most existing approaches operate directly at RTL. We ask whether agents can design better chips by leveraging higher-level abstractions. We compare Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and combine Agent-based HLS Design with Post-HLS RTL Refinement as Agent-based HLS with RTL Refinement (AHRR). We use FPGAs as a practical, easy-to-deploy platform for end-to-end evaluation, but note that the design-flow tradeoffs we study are largely independent of the target technology. Across a diverse 11-tasks benchmark suite, AHRR achieves a 2.6

\times

geometric-mean speedup over Direct RTL Design across our benchmark suite. Case studies show that HLS distills design knowledge into abstractions that agents can leverage, while RTL refinement recovers lower-level optimization opportunities. Together, these results make AHRR a promising workflow for agentic chip design. The code and evaluation artifacts are available at https://github.com/ZijD/AHRR.

Abstract

Electronic Design Automation

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