Agent Factories for High Level Synthesis: How Far Can General-Purpose Coding Agents Go in Hardware Optimization?
Organizations: IBM Corporation
Abstract
We present an empirical study of how far general-purpose coding agents -- without hardware-specific training -- can optimize hardware designs from high-level algorithmic specifications. We introduce an agent factory, a two-stage pipeline that constructs and coordinates multiple autonomous optimization agents. In Stage1, the pipeline decomposes a design into sub-kernels, independently optimizes each using pragma and code-level transformations, and formulates an Integer Linear Program (ILP) to assemble globally promising configurations under an area constraint. In Stage2, it launches expert agents over the top ILP solutions, each exploring cross-function optimizations such as pragma recombination, loop fusion, and memory restructuring that are not captured by sub-kernel decomposition. We evaluate the approach on 12 kernels from HLS-Eval and Rodinia-HLS using Claude Code (Opus~4.5/4.6) with AMD Vitis HLS. Scaling from 1 to 10 agents yields a mean speedup over baseline, with larger gains on harder benchmarks: streamcluster exceeds and kmeans reaches approximately . Across benchmarks, agents consistently rediscover known hardware optimization patterns without domain-specific training, and the best designs often do not originate from top-ranked ILP candidates, indicating that global optimization exposes improvements missed by sub-kernel search. These results establish agent scaling as a practical and effective axis for HLS optimization.
Figures & tables
| Variant | Strategy |
|---|---|
| Baseline: synthesize unmodified code | |
| Conservative: minimal pragmas, low area | |
| Pipeline: PIPELINE II | |
| Aggressive: pipeline + partial/full UNROLL | |
| Alternate: ARRAY_PARTITION , INLINE , | |
| closed-form rewrites |
| 1 2 | 2 4 | 4 8 | 8 10 | |
|---|---|---|---|---|
| Speedup | 4.31 (+5.9%) | 4.92 (+14.2%) | 7.07 (+43.7%) | 6.53 (-7.6%) |
| DFG | Agent-formulated ILP & constraints |
|---|---|
| s.t. One variant per function; is variant area. | |
| s.t. denote latencies of F and O. | |
| denote module latencies. | |
| denotes module latency. |
Appendix figures & tables1 asset
Supplementary material from the paper’s appendix.
Appendix
Electronic Design Automation
Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.
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